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| 8 bit microcontroller tlcs-870/x series TMP88FW45AFG
the information contained herein is subject to change without notice. 021023_d toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property.in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent tosh- iba products specifications. also, please keep in mind the precautions and conditions set forth in the handling guide for sem- iconductor devices, or toshiba semiconductor reliability handbook etc. 021023_a the toshiba products listed in this document are intended for usage in general electronics appli- cations (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (unintended usage). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer's own risk. 021023_b the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_q the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. 070122_c for a discussion of how the reliability of microcontrollers can be predicted, please refer to section 1.3 of the chapter entitled quality and reliability assurance/handling precautions. 030619_s ? 2008 toshiba corporation all rights reserved difference between tmp88fw45fg and TMP88FW45AFG in TMP88FW45AFG, all sfr/dbr/ebr registers except the oscillation frequency detector are mapped to the same address as tmp88fw45fg. therefore, the software for tmp88fw45fg can be used in TMP88FW45AFG. as the oscillation frequency detector is not available in emulator (bm88fw44f0a-m15), please use the flash product (TMP88FW45AFG) to check the oscillation frequency detection. products name tmp88fw45 tmp88fw45a rom 122880 bytes (flash) ram 4224 bytes dbr/ebr 144 bytes 144 bytes registers of oscillation frequency detector are included i/o port 71 pins high-current port 24 pins (sink open drain) interrupt external: 5 interrupts, internal: 31 interrupts timer/counter 16-bit: 2 channels 8-bit: 4 channels pmd 2 channel uart 2 channels sio 1 channels 8-bit high-speed pwm 2 channels 10-bit ad converter 16 channels oscillation frequency detectior non available available flash security read protect "write protect" has been added in "read protect". and the name of read protect has been changed to "security program". flash size code in product id 0eh 1dh the number of flash cell 2 1 (note 1) flash programming adapter pn410104 structuer of test pin absolute maximum ratin of power supply (vdd) 6.5v 6.0v operating condition (mcu mode) read/fetch 4.5v to 5.5v at 20mhz (-40 to 85 c) program/erase 4.5v to 5.5v at 20mhz (-10 to 40 c) operating condition (serial prom mode) 4.5v to 5.5v at 20mhz (-10 to 40 c) note 1: the same command sequence of tmp88fw45fg can be used in TMP88FW45AFG. TMP88FW45AFG r without protect diode on the vdd side r vdd TMP88FW45AFG revision history date revision comment 2008/5/29 tentative 1 first release 2008/10/24 2 contents revised table of contents difference between tmp88fw45fg and TMP88FW45AFG TMP88FW45AFG 1.1 features...................................................................................................................................... 1 1.2 pin assignment.......................................................................................................................... 3 1.3 block diagram........................................................................................................................... 4 1.4 pin names and functions.......................................................................................................... 5 2. functional description 2.1 functions of the cpu core........................................................................................................ 9 2.1.1 memory address map......................................................................................................................................................... 9 2.1.2 program memory (rom).................................................................................................................................................. 10 2.1.3 data memory (ram)........................................................................................................................................................ 10 2.1.4 system clock control circuit............................................................................................................................................ 11 2.1.4.1 clock generator 2.1.4.2 timing generator 2.1.4.3 standby control circuit 2.1.4.4 controlling operation modes 2.1.5 reset circuit...................................................................................................................................................................... 23 2.1.5.1 external reset input 2.1.5.2 address trap reset 2.1.5.3 watchdog timer reset 2.1.5.4 system clock reset 2.1.5.5 oscillation frequency detection reset 3. interrupt control circuit 3.1 interrupt latches (il39 to il2) ................................................................................................ 26 3.2 interrupt enable register (eir) ................................................................................................ 27 3.2.1 interrupt master enable flag (imf) ................................................................................................................................... 27 3.2.2 individual interrupt enable flags (ef39 to ef3) ............................................................................................................... 27 3.3 interrupt sequence ................................................................................................................. 30 3.3.1 interrupt acceptance processing is packaged as follows. .................................................................................................. 30 3.3.2 saving/restoring general-purpose registers ....................................................................................................................... 31 3.3.2.1 using automatic register bank switching 3.3.2.2 using register bank switching 3.3.2.3 using push and pop instructions 3.3.2.4 using data transfer instructions 3.3.3 interrupt return .................................................................................................................................................................. 33 3.4 software interrupt (intsw) ................................................................................................... 34 3.4.1 address error detection ..................................................................................................................................................... 34 3.4.2 debugging ......................................................................................................................................................................... 34 3.5 external interrupts .................................................................................................................. 35 i 4. special function register 4.1 sfr.......................................................................................................................................... 37 4.2 ebr.......................................................................................................................................... 39 4.3 dbr......................................................................................................................................... 40 5. input/output ports 5.1 port p0 (p03 to p00)................................................................................................................ 45 5.2 port p1 (p17 to p10) ............................................................................................................... 47 5.3 port p2 (p22 to p20) ............................................................................................................... 48 5.4 port p3 (p37 to p30) ............................................................................................................... 50 5.5 port p4 (p47 to p40) ............................................................................................................... 52 5.6 port p5 (p57 to p50) ............................................................................................................... 54 5.7 port p6 (p67 to p60) ............................................................................................................... 56 5.8 port p7 (p77 to p70) ............................................................................................................... 58 5.9 port p8 (p87 to p80)................................................................................................................ 60 5.10 port p9 (p97 to p90).............................................................................................................. 62 6. time base timer (tbt) and divider output ( dvo) 6.1 time base timer..................................................................................................................... 65 6.2 divider output (dvo).............................................................................................................67 7. watchdog timer (wdt) 7.1 watchdog timer configuration ..............................................................................................69 7.2 watchdog timer control ........................................................................................................ 70 7.2.1 malfunction detection methods using the watchdog timer .......................................................................................... 70 7.2.2 watchdog timer enable ................................................................................................................................................... 71 7.2.3 watchdog timer disable .................................................................................................................................................. 72 7.2.4 watchdog timer interrupt (intwdt) ............................................................................................................................. 72 7.2.5 watchdog timer reset ..................................................................................................................................................... 73 8. oscillation frequency detector 8.1 configuration........................................................................................................................... 75 8.2 control..................................................................................................................................... 76 8.3 function................................................................................................................................... 77 8.3.1 enabling and disabling the oscillation frequency detection........................................................................................... 77 8.3.2 setting the lower and higher frequency for detection.................................................................................................... 78 8.3.3 oscillation frequency detection reset ............................................................................................................................. 78 9. 16-bit timercounter 1 (tc1) 9.1 configuration .......................................................................................................................... 81 ii 9.2 timercounter control............................................................................................................. 82 9.3 function................................................................................................................................... 84 9.3.1 timer mode........................................................................................................................................................................ 84 9.3.2 external trigger timer mode............................................................................................................................................86 9.3.3 event counter mode..........................................................................................................................................................88 9.3.4 window mode................................................................................................................................................................... 89 9.3.5 pulse width measurement mode.......................................................................................................................................90 9.3.6 programmable pulse generate (ppg) output mode......................................................................................................... 93 10. 16-bit timer (ctc) 10.1 configuration......................................................................................................................... 95 10.2 control................................................................................................................................... 96 10.3 function................................................................................................................................. 99 10.3.1 timer mode with software start....................................................................................................................................... 99 10.3.2 timer mode with external trigger start.......................................................................................................................... 100 10.3.3 event counter mode....................................................................................................................................................... 101 10.3.4 programmable pulse generate (ppg) output mode.......................................................................................................102 11. 8-bit timercounter 3 (tc3) 11.1 configuration ...................................................................................................................... 107 11.2 timercounter control ........................................................................................................ 108 11.3 function .............................................................................................................................. 109 11.3.1 timer mode ...................................................................................................................................................................109 11.3.2 event counter mode ..................................................................................................................................................... 111 11.3.3 capture mode................................................................................................................................................................ 112 12. 8-bit timercounter 4 (tc4) 12.1 configuration ...................................................................................................................... 113 12.2 timercounter control ........................................................................................................ 114 12.3 function............................................................................................................................... 115 12.3.1 timer mode................................................................................................................................................................... 115 12.3.2 event counter mode ..................................................................................................................................................... 115 12.3.3 programmable divider output (pdo) mode................................................................................................................. 115 12.3.4 pulse width modulation (pwm) output mode............................................................................................................ 116 13. 8-bit timercounter 5,6(tc5, 6) 13.1 configuration....................................................................................................................... 119 13.2 timercounter control......................................................................................................... 120 13.3 function............................................................................................................................... 123 13.3.1 8-bit timer mode (tc5 and 6)...................................................................................................................................... 123 13.3.2 8-bit event counter mode (tc5, 6).............................................................................................................................. 124 13.3.3 8-bit programmable divider output (pdo) mode (tc5, 6)......................................................................................... 124 13.3.4 8-bit pulse width modulation (pwm) output mode (tc5, 6).................................................................................... 127 13.3.5 16-bit timer mode (tc5 and 6).................................................................................................................................... 129 13.3.6 16-bit event counter mode (tc5 and 6)...................................................................................................................... 130 13.3.7 16-bit pulse width modulation (pwm) output mode (tc5 and 6)............................................................................. 130 13.3.8 16-bit programmable pulse generate (ppg) output mode (tc5 and 6)...................................................................... 133 iii 14. motor control circuit (pmd: programmable motor driver) 14.1 outline of motor control..................................................................................................... 136 14.2 configuration of the motor control circuit........................................................................ 138 14.3 position detection unit........................................................................................................ 139 14.3.1 configuration of the position detection unit.................................................................................................................. 140 14.3.2 position detection circuit register functions............................................................................................................... 141 14.3.3 outline processing in the position detection unit........................................................................................................ 145 14.4 timer unit........................................................................................................................... 146 14.4.1 configuration of the timer unit.................................................................................................................................... 147 14.4.1.1 timer circuit register functions 14.4.1.2 outline processing in the timer unit 14.5 three-phase pwm output unit........................................................................................... 152 14.5.1 configuration of the three-phase pwm output unit...................................................................................................... 152 14.5.1.1 pulse width modulation circuit (pwm waveform generating unit) 14.5.1.2 commutation control circuit 14.5.2 register functions of the waveform synthesis circuit................................................................................................. 156 14.5.3 port output as set with uoc/voc/woc bits and upwm/vpwm/wpwm bits........................................................ 159 14.5.4 protective circuit........................................................................................................................................................... 161 14.5.5 functions of protective circuit registers...................................................................................................................... 163 14.6 electrical angle timer and waveform arithmetic circuit................................................. 165 14.6.1 electrical angle timer and waveform arithmetic circuit........................................................................................... 166 14.6.1.1 functions of the electrical angle timer and waveform arithmetic circuit registers 14.6.1.2 list of pmd related control registers 15. asynchronous serial interface (uart1) 15.1 configuration....................................................................................................................... 179 15.2 control ................................................................................................................................ 180 15.3 transfer data format........................................................................................................... 183 15.4 transfer rate....................................................................................................................... 184 15.5 data sampling method........................................................................................................ 184 15.6 stop bit length................................................................................................................. 185 15.7 parity.................................................................................................................................... 185 15.8 transmit/receive operation................................................................................................ 185 15.8.1 data transmit operation............................................................................................................................................... 185 15.8.2 data receive operation................................................................................................................................................. 185 15.9 status flag........................................................................................................................... 186 15.9.1 parity error.................................................................................................................................................................... 186 15.9.2 framing error................................................................................................................................................................ 186 15.9.3 overrun error................................................................................................................................................................. 186 15.9.4 receive data buffer full............................................................................................................................................... 187 15.9.5 transmit data buffer empty......................................................................................................................................... 187 15.9.6 transmit end flag......................................................................................................................................................... 188 16. asynchronous serial interface (uart2) 16.1 configuration....................................................................................................................... 189 16.2 control ................................................................................................................................ 190 16.3 transfer data format........................................................................................................... 192 16.4 transfer rate....................................................................................................................... 193 16.5 data sampling method........................................................................................................ 193 16.6 stop bit length................................................................................................................. 194 iv 16.7 parity.................................................................................................................................... 194 16.8 transmit/receive operation................................................................................................ 194 16.8.1 data transmit operation............................................................................................................................................... 194 16.8.2 data receive operation................................................................................................................................................. 194 16.9 status flag........................................................................................................................... 195 16.9.1 parity error.................................................................................................................................................................... 195 16.9.2 framing error................................................................................................................................................................ 195 16.9.3 overrun error.................................................................................................................................................................195 16.9.4 receive data buffer full............................................................................................................................................... 196 16.9.5 transmit data buffer empty......................................................................................................................................... 196 16.9.6 transmit end flag......................................................................................................................................................... 197 17. synchronous serial interface (sio) 17.1 configuration....................................................................................................................... 199 17.2 control................................................................................................................................. 200 17.3 serial clock.......................................................................................................................... 202 17.3.1 clock source.................................................................................................................................................................. 202 17.3.1.1 internal clock 17.3.1.2 external clock 17.3.2 shift edge....................................................................................................................................................................... 203 17.3.2.1 leading edge 17.3.2.2 trailing edge 17.4 number of bits to transfer.................................................................................................... 203 17.5 number of words to transfer................................................................................................ 203 17.6 transfer mode..................................................................................................................... 204 17.6.1 4-bit and 8-bit transfer modes........................................................................................................................................ 204 17.6.2 4-bit and 8-bit receive modes......................................................................................................................................... 206 17.6.3 8-bit transfer / receive mode.......................................................................................................................................... 207 18. 10-bit ad converter (adc) 18.1 configuration....................................................................................................................... 211 18.2 register configuration......................................................................................................... 212 18.3 function.............................................................................................................................. 215 18.3.1 software start mode...................................................................................................................................................... 215 18.3.2 repeat mode.................................................................................................................................................................. 215 18.3.2.1 register setting 18.4 stop mode during ad conversion.................................................................................... 217 18.5 analog input voltage and ad conversion result.............................................................. 218 18.6 precautions about ad converter......................................................................................... 219 18.6.1 analog input pin voltage range......................................................................................................................................219 18.6.2 analog input shared pins............................................................................................................................................... 219 18.6.3 noise countermeasure................................................................................................................................................... 219 19. 8-bit high-speed pwm ( hpwm0 and hpwm1) 19.1 configuration....................................................................................................................... 221 19.2 control................................................................................................................................. 222 19.3 functional description......................................................................................................... 222 19.3.1 operation modes............................................................................................................................................................ 222 19.3.1.1 8-bit mode 19.3.1.2 7-bit mode 19.3.1.3 6-bit mode 19.3.2 setting output data......................................................................................................................................................... 225 v 20. flash memory 20.1 flash memory control......................................................................................................... 228 20.1.1 flash memory command sequence execution control (flscr 22. input/output circuitry 22.1 control pins......................................................................................................................... 267 22.2 input/output ports................................................................................................................. 267 23. electrical characteristics 23.1 absolute maximum ratings................................................................................................ 269 23.2 operating conditions........................................................................................................... 270 23.2.1 mcu mode (flash programming or erasing) ............................................................................................................... 270 23.2.2 mcu mode (except flash programming or erasing) ................................................................................................... 271 23.2.3 serial prom mode........................................................................................................................................................ 271 23.3 dc characteristics .............................................................................................................. 272 23.4 ad characteristics............................................................................................................... 273 23.5 ac characteristics............................................................................................................... 273 23.6 oscillation frequency detection ac characteristics.......................................................... 274 23.7 flash characteristics............................................................................................................ 274 23.8 recommended oscillating conditions................................................................................ 275 23.9 handling precaution............................................................................................................ 275 24. package dimensions vii viii cmos 8-bit microcontroller TMP88FW45AFG product no. rom (flash) ram package TMP88FW45AFG 122880 bytes 4224 bytes qfp80-p-1420-0.80b 1.1 features 1. 8-bit single chip microcomputer tlcs-870/x series - instruction execution time : 0.20 s (at 20 mhz) - 181 types & 842 basic instructions 2. 36 interrupt sources (external : 5 internal : 31) 3. input / output ports (71 pins) large current output: 24pins (typ. 20ma), led direct drive 4. prescaler - time base timer divider output function (dvo) 5. watchdog timer select of "internal reset request" or "interrupt request". 6. oscillation frequency detector : 1ch 7. 16-bit timer counter: 1 ch - timer, external trigger, window, pulse width measurement, event counter, programmable pulse generate (ppg) modes 8. 16-bit timer/counter(ctc): 1ch - ctc:timer,event counter or ppg (programmable pulse) output 9. 8-bit timer counter : 1 ch this product uses the super flash? technology under the licence of silicon storage technology, inc. super flash? is registered trademark of silicon storage technology, inc. ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to prop- erty.in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the handling guide for semiconductor devices, or toshiba semiconductor reliability handbook etc. 021023_a ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (unintended usage). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer's own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/ or sale are prohibited under any applicable laws and regulations. 060106_q ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. 070122_c ? for a discussion of how the reliability of microcontrollers can be predicted, please refer to section 1.3 of the chapter entitled quality and reliability assurance/handling precautions. 030619_s TMP88FW45AFG page 1 - timer, event counter, capture modes 10. 8-bit timer counter : 1 ch - timer, event counter, pulse width modulation (pwm) output, programmable divider output (pdo) modes 11. 8-bit timer counter : 2 ch - timer, event counter, programmable divider output (pdo), pulse width modulation (pwm) output, programmable pulse generation (ppg) modes 12. programmable motor driver (pmd) : 2 ch - sine wave drive circuit (built-in sine wave data-table ram) rotor position detect function motor control timer and capture function overload protective function auto commutation and auto position detection start function 13. 8-bit uart : 2 ch 14. 8-bit sio: 1 ch 15. 10-bit successive approximation type ad converter - analog input: 16 ch 16. 8-bit high-speed pwm ( hpwm0 and hpwm1) 17. clock oscillation circuit : 1 set 18. low power consumption operation (2 modes) - stop mode: oscillation stops. (battery/capacitor back-up.) - idle mode: cpu stops. only peripherals operate using high frequency clock. release by interrupts (cpu restarts). 19. operation voltage: 4.5 v to 5.5 v at 20mhz TMP88FW45AFG 1.1 features page 2 1.2 pin assignment p03 ( hpwm1) p02 ( hpwm0) p01 (txd2/ pdo6/pwm6/ppg6) p00 (rxd2/tc6) p97 p96 p95 p94 p93 p92 p91 p90 p87 p86 p85 p84 p83 p82 p81 (txd3) p80 (rxd3) avss avdd varef p77 (ain15/dbout2) ( int0) p10 p76 (ain14) (int1) p11 p75 (ain13) (tc1/int2) p12 p74 (ain12) (tc5/ dvo) p13 p73 (ain11) ( pwm5/pdo5/ ppg1) p14 p72 (ain10) (pdu2) p15 p71 (ain9) (pdv2) p16 p70 (ain8) (pdw2) p17 p67 (ain7/dbout1) ( cl2) p50 p66 (ain6) ( emg2) p51 p65 (ain5) (u2) p52 p64 (ain4) (v2) p53 p63 (ain3) (w2) p54 p62 (ain2) (x2) p55 p61 (ain1) (y2) p56 p60 (ain0) (z2) p57 p47 (ctc) vss xin xout test vdd (tc3) p21 ( pwm4/pdo4/tc4/int4) p22 reset ( stop/ int5) p20 (z1) p30 (y1) p31 (x1) p32 (w1) p33 (v1) p34 (u1) p35 ( emg1) p36 ( cl1) p37 (pdw1) p40 (pdv1) p41 (pdu1) p42 ( sck) p43 (boot/si/rxd1) p44 (so/txd1) p45 ( ppg2) p46 figure 1-1 pin assignment TMP88FW45AFG page 3 1.3 block diagram figure 1-2 block diagram TMP88FW45AFG 1.3 block diagram page 4 1.4 pin names and functions the TMP88FW45AFG has mcu mode, parallel prom mode, and serial prom mode. table 1-1 shows the pin functions in mcu mode. the serial prom mode is explained later in a separate chapter. table 1-1 pin names and functions (1/4) pin name pin number input/output functions p03 hpwm1 64 io o port03 high-spped pwm1 output p02 hpwm0 63 io o port02 high-spped pwm0 output p01 txd2 pdo6/pwm6/ppg6 62 io o o port01 uart data output 2 pdo6/pwm6/ppg6 output p00 rxd2 tc6 61 io i i port00 uart data input 2 tc6 input p17 pdw2 72 io i port17 pmd control input w2 p16 pdv2 71 io i port16 pmd control input v2 p15 pdu2 70 io i port15 pmd control input u2 p14 ppg1 pwm5/pdo5 69 io o o port14 ppg1 output pwm5/pdo5 output p13 dvo tc5 68 io o i port13 divider output tc5 input p12 int2 tc1 67 io i i port12 external interrupt 2 input tc1 input p11 int1 66 io i port11 external interrupt 1 input p10 int0 65 io i port10 external interrupt 0 input p22 int4 tc4 pwm4/pdo4 7 io i i o port22 external interrupt 4 input tc4 input pwm4/pdo4 output p21 tc3 6 io i port21 tc3 pin input p20 int5 stop 9 io i i port20 external interrupt 5 input stop mode release signal input p37 cl1 17 io i port37 pmd over load protection input1 TMP88FW45AFG page 5 table 1-1 pin names and functions (2/4) pin name pin number input/output functions p36 emg1 16 io i port36 pmd emergency stop input1 p35 u1 15 io o port35 pmd control output u1 p34 v1 14 io o port34 pmd control output v1 p33 w1 13 io o port33 pmd control output w1 p32 x1 12 io o port32 pmd control output x1 p31 y1 11 io o port31 pmd control output y1 p30 z1 10 io o port30 pmd control output z1 p47 ctc 25 i i port47 ctc input p46 ppg2 24 io o port46 ppg2 p45 txd1 so 23 io o o port45 uart data output 1 serial data output p44 rxd1 si boot 22 io i i i port44 uart data input 1 serial data input serial prom mode control input p43 sck 21 io io port43 serial clock i/o p42 pdu1 20 io i port42 pmd control input u1 p41 pdv1 19 io i port41 pmd control input v1 p40 pdw1 18 io i port40 pmd control input w1 p57 z2 80 io o port57 pmd control output z2 p56 y2 79 io o port56 pmd control output y2 p55 x2 78 io o port55 pmd control output x2 p54 w2 77 io o port54 pmd control output w2 TMP88FW45AFG 1.4 pin names and functions page 6 table 1-1 pin names and functions (3/4) pin name pin number input/output functions p53 v2 76 io o port53 pmd control output v2 p52 u2 75 io o port52 pmd control output u2 p51 emg2 74 io i port51 pmd emergency stop input2 p50 cl2 73 io i port50 pmd over load protection input2 p67 ain7 dbout1 33 io i o port67 analog input7 pmd debug output1 p66 ain6 32 io i port66 analog input6 p65 ain5 31 io i port65 analog input5 p64 ain4 30 io i port64 analog input4 p63 ain3 29 io i port63 analog input3 p62 ain2 28 io i port62 analog input2 p61 ain1 27 io i port61 analog input1 p60 ain0 26 io i port60 analog input0 p77 ain15 dbout2 41 io i o port77 analog input15 pmd debug output2 p76 ain14 40 io i port76 analog input14 p75 ain13 39 io i port75 analog input13 p74 ain12 38 io i port74 analog input12 p73 ain11 37 io i port73 analog input11 p72 ain10 36 io i port72 analog input10 p71 ain9 35 io i port71 analog input9 p70 ain8 34 io i port70 analog input8 TMP88FW45AFG page 7 table 1-1 pin names and functions (4/4) pin name pin number input/output functions p87 52 io port87 p86 51 io port86 p85 50 io port85 p84 49 io port84 p83 48 io port83 p82 47 io port82 p81 txd3 46 io i port81 uart data output 3 p80 rxd3 45 io i port80 uart data input 3 p97 60 io port97 p96 59 io port96 p95 58 io port95 p94 57 io port94 p93 56 io port93 p92 55 io port92 p91 54 io port91 p90 53 io port90 xin 2 i resonator connecting pins for high-frequency clock xout 3 o resonator connecting pins for high-frequency clock reset 8 i reset signal test 4 i test pin for out-going test and the serial prom mode control pin. usually fix to low level. fix to high level when the serial prom mode starts. varef 42 i analog base voltage input pin for a/d conversion avdd 43 i analog power supply avss 44 i analog power supply vdd 5 i +5v vss 1 i 0(gnd) TMP88FW45AFG 1.4 pin names and functions page 8 2. functional description 2.1 functions of the cpu core the cpu core consists mainly of the cpu, system clock control circuit, and interrupt control circuit. this chapter describes the cpu core, program memory, data memory, and reset circuit of the TMP88FW45AFG. 2.1.1 memory address map the memory of the TMP88FW45AFG consists of four blocks: rom, ram, sfr (special function registers), and dbr/ebr (data buffer registers), which are mapped into one 1-mbyte address space. the general-purpose registers consist of 16 banks, which are mapped into the ram address space. figure 2-1 shows a memory address map of the TMP88FW45AFG. figure 2-1 memory address map TMP88FW45AFG page 9 vector table for vector call instructions interrupt vector table interrupt vector table program memory rom ( bytes) ram ( bytes) ram (128 bytes) sfr rom: read-only memory program memory vector table sfr: special function registers input/output port peripheral hardware control register peripheral hardware status register system control register interrupt control register program status word dbr: data buffer registers input/output port peripheral hardware control registe r peripheral hardware status register ram: random access memory data memory stack general-purpose register bank random-access memory special function register general-purpose register bank (8 registers 16 banks) data buffer register (peripheral hardware control register / status register) 64 bytes 64 bytes 64 bytes 128 bytes bytes bytes 128 bytes 00000h 000c0h 000bfh 04000h 0003fh 00040h 01fffh fffffh fff7fh fff80h fff40h fff00h fff3fh bytes 4k 4096 120k 122624 dbr/ebr 01f70h 21effh ebr: extra data buffer registers input/output port peripheral hardware control register peripheral hardware status register 010bfh 144 2.1.2 program memory (rom) the TMP88FW45AFG contains 120kbytes program memory (flash) located at addresses 04000h to 21effh and addresses fff00h to fffffh. 2.1.3 data memory (ram) the TMP88FW45AFG contains 4kbytes +128bytes ram. the first 128bytes location (00040h to 000bfh) of the internal ram is shared with a general-purpose register bank. the content of the data memory is indeterminate at power-on, so be sure to initialize it in the initialize rou- tine . example :clearing the internal ram of the TMP88FW45AFG (clear all ram addresses to 0, except bank 0) ld hl, 0048h ; set the start address ld a, 00h ; set the initialization data (00h) ld bc, 1077h ; set byte counts (-1) sramclr: ld (hl+), a dec bc jrs f, sramclr note: because general-purpose registers exist in the ram, never clear the current bank address of ram. in the above example, the ram is cleared except bank 0. TMP88FW45AFG 2. functional description 2.1 functions of the cpu core page 10 2.1.4 system clock control circuit the system clock control circuit consists of a clock generator, timing generator, and standby control circuit. figure 2-2 system clock control circuit 2.1.4.1 clock generator the clock generator generates the fundamental clock which serves as the reference for the system clocks supplied to the cpu core and peripheral hardware units. the high-frequency clock (frequency fc) can be obtained easily by connecting a resonator to the xin and xout pins. or a clock generated by an external oscillator can also be used. in this case, enter the external clock from the xin pin and leave the xout pin open. the TMP88FW45AFG does not support the cr network that produces a time constant. figure 2-3 example for connecting a resonator adjusting the oscillation frequency note:although no hardware functions are provided that allow the fundamental clock to be monitored directly from the outside, the oscillation frequency can be adjusted by forwarding the pulse of a fixed frequency (e.g., clock output) to a port and monitoring it in a program while interrupts and the watchdog timer are disabled. for systems that require adjusting the oscillation frequency, an adjustment program must be created beforehand. 2.1.4.2 timing generator the timing generator generates various system clocks from the fundamental clock that are supplied to the cpu core and peripheral hardware units. the timing generator has the following functions: 1. generate a divider output ( dvo) pulse TMP88FW45AFG page 11 xin high-frequency clock xout (a) using a crystal or ceramic resonator xin xout (b) using an external oscillator (open) timing generator standby control circuit high-frequency clock oscillator circuit tbtcr syscr2 syscr1 xin xout clock generator fc 00036h 00038h 00039h system clocks timing generator control register system control register 2. generate the source clock for the time base timer 3. generate the source clock for the watchdog timer 4. generate the internal source clock for the timer counter 5. generate a warm-up clock when exiting stop mode (1) configuration of the timing generator the timing generator a 3-stage prescaler, 21-stage dividers, and a machine cycle counter. when reset and when entering/exiting stop mode, the prescaler and dividers are cleared to 0. figure 2-4 configuration of the timing generator TMP88FW45AFG 2. functional description 2.1 functions of the cpu core page 12 dv1ck fc prescaler divider divider selector timer counter machine cycle counter 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 s a y b 6 5 4 3 2 1 1 2 0 standby control circuit watchdog timer time base timer divider output etc. divider control register cgcr (0030h) 7 6 5 4 3 2 1 0 0 0 dv1ck 0 0 0 (initial value: 000* *000) dv1ck selects input clock to the first di- vider stage 0: fc/4 1: fc/8 r/w note 1: fc: the high-frequency clock [hz], *: dont care note 2: the cgcr register bits 4 and 3 show an indeterminate value when read. note 3: be sure to write 0 to cgcr register bits 7, 6, 2, 1 and 0. timing generator control register tbtcr (0036h) 7 6 5 4 3 2 1 0 dvoen dvock 0 tbten tbtck (initial value: 0000 0000) note 1: *: dont care note 2: be sure to write 0 to tbtcr register bit 4. (2) machine cycle instruction execution and the internal hardware operations are synchronized to the system clocks. the minimum unit of instruction execution is referred to as the machine cycle. the tlcs-870/x series has 15 types of instructions, from 1-cycle instructions which are executed in one machine cycle up to 15-cycle instructions that require a maximum of 15 machine cycles. a machine cycle consists of four states (s0 to s3), with each state comprised of one main system clock cycle. figure 2-5 machine cycles TMP88FW45AFG page 13 main system clock states s0 s1 s2 s3 s0 s1 s2 s3 1/fc (0.20 s at 20 mhz) machine cycle 2.1.4.3 standby control circuit the standby control circuit starts/stops the high-frequency clock oscillator circuit and selects the main system clock. the system control registers (syscr1, syscr2) are used to control operation modes of this circuit. figure 2-6 shows an operation mode transition diagram, followed by description of the system control registers. (1) single clock mode only the high-frequency clock oscillator circuit is used. because the main system clock is generated from the high-frequency clock, the machine cycle time in single clock mode is 4/fc [s]. 1. normal mode in this mode, the cpu core and peripheral hardware units are operated with the high-fre- quency clock. the TMP88FW45AFG enters this normal mode after reset. 2. idle mode in this mode, the cpu and watchdog timer are turned off while the peripheral hardware units are operated with the high-frequency clock. idle mode is entered into by using system control register 2. the device is placed out of this mode and back into normal mode by an interrupt from the peripheral hardware or an external interrupt. when imf (interrupt master enable flag) = 1 (interrupt enabled), the device returns to normal operation after the interrupt has been serviced. when imf = 0 (interrupt disabled), the device restarts execution beginning with the instruction next to one that placed it in idle mode. 3. stop mode the entire system operation including the oscillator circuit is halted, retaining the internal state immediately before being stopped, with a minimal amount of power consumed. stop mode is entered into by using system control register 1, and is exited by stop pin input (level or edge selectable). after an elapse of the warm-up time, the device restarts exe- cution beginning with the instruction next to one that placed it in stop mode. table 2-1 single clock mode operation mode oscillator circuit cpu core peripheral circuit machine cycle time high frequency low frequency single clock reset oscillate - reset reset 4/fc [s] normal operate operate idle stop stop stop stop - figure 2-6 operation mode transition diagram TMP88FW45AFG 2. functional description 2.1 functions of the cpu core page 14 reset stop mode normal mode idle mode interrupt instruction input for releasing mode instruction reset deasserted system control register 1 syscr1 (0038h) 7 6 5 4 3 2 1 0 stop relm retm outen wut (initial value: 0000 00**) stop place the device in stop mode 0: keep the cpu core and peripheral hardware operating 1: stop the cpu core and peripheral hardware (placed in stop mode) r/w relm select method by which the de- vice is released from stop mode 0: released by a rising edge on stop pin input 1: released by a high level on stop pin input retm select operation mode after ex- iting stop mode 0: returns to normal mode 1: reserved outen select port output state during stop mode 0: high-impedance state 1: hold output wut unit of warm-up time when ex- iting stop mode when returning to normal mode dv1ck = 0 dv1ck = 1 00 3 2 16 /fc 3 2 17 /fc 01 2 16 /fc 2 17 /fc 10 2 14 /fc 2 15 /fc 11 reserved reserved note 1: when entering from normal mode into stop mode, always be sure to set syscr1 2.1.4.4 controlling operation modes (1) stop mode stop mode is controlled by system control register 1 (syscr1) and the stop pin input. the stop pin is shared with p20 port and int5 (external interrupt input 5). stop mode is entered into by setting stop (syscr1 register bit 7) to 1. during stop mode, the device retains the following state. 1. stop oscillation, thereby stopping operation of all internal circuits. 2. the data memory, register, program status word, and port output latch hold the state in which they were immediately before entering stop mode. 3. clear the prescaler and divider for the timing generator to 0. 4. the program counter holds the instruction address two instructions ahead the one that placed the device in stop mode (e.g., set (syscr1).7). the device is released from stop mode by the active level or edge on stop pin input as selected by syscr1 figure 2-7 released from stop mode by level note 1: once warm-up starts, the device does not return to stop mode even when the stop pin input is pulled low again. note 2: if relm is changed to 1 (level mode) after being set to 0 (edge mode), stop mode remains unchanged unless a rising edge on stop pin input is detected. a. released by edge (when relm = 0) the device is released from stop mode by a rising edge on stop pin input. this method is used in applications where a relatively short time of program processing is repeated at certain fixed intervals. apply a fixed-period signal (e.g., clock from the low-power oscillating source) to the stop pin. when relm = 0 (edge mode), the device is placed in stop mode even when the stop pin input level is high. example :entering stop mode from normal mode di ; imf 0 ld (syscr1) , 10010000b ; set to be released by edge when entering stop mode figure 2-8 released from stop mode by edge TMP88FW45AFG page 17 stop pin xout pin normal operation v ih stop mode warm-up stop mode placed into stop mode in a program released from stop mode in hardware by a rising edge on stop pin input. normal operation stop pin xout pin normal operation released from stop mode in hardware normal operation v ih stop mode warm-up detect low on stop pin input in a program before entering stop mode always released by a high level on stop pin input the device is released from stop mode following the sequence described below. 1. only the high-frequency oscillator is oscillating. 2. a warm-up time is inserted in order to allow for the clock oscillation to stabilize. during warm- up, the internal circuits remain idle. the warm-up time can be selected from three choices according to the oscillator characteristics by using syscr1 figure 2-9 entering and exiting stop mode (when dv1ck = 0) TMP88FW45AFG page 19 oscillation instruction execution divider (a) entering stop mode (example: entered into by the set (syscr1). 7 instruction placed at address a) main system clock main system clock program counter stop stop a + 2 a + 3 n n + 1 n + 2 n + 3 n + 4 0 set (syscr1). 7 oscillator circuit oscillator circuit warm-up (b) exiting stop mode oscillation instruction execution divider program counter stop stop count up 0 0 1 2 3 a + 3 instruction at address a + 4 instruction at address a + 3 instruction at address a + 2 stop pin input a + 4 a + 5 a + 6 (2) idle mode idle mode is controlled by system control register 2 (syscr2) and a maskable interrupt. during idle mode, the device retains the following state. 1. the cpu and watchdog timer stop operating. the peripheral hardware continues operating. 2. the data memory, register, program status word, and port output latch hold the state in which they were immediately before entering idle mode. 3. the program counter holds the instruction address two instructions ahead the one that placed the device in idle mode. example :placing the device in idle mode set (syscr2) . 4 figure 2-10 idle mode TMP88FW45AFG 2. functional description 2.1 functions of the cpu core page 20 place the device in idle mode (by instruction) stop the cpu and wdt interrupt handling execute the instruction next to one that placed device idle mode reset ye s no no no interrupt request ? imf = 1 reset input ? ye s yes (released by interrupt) (released normally) the device can be released from idle mode normally or by an interrupt as selected with the interrupt master enable flag (imf). a. released normally (when imf = 0) the device can be released from idle mode by the interrupt source enabled by the interrupt individual enable flag (ef), and restarts execution beginning with the instruction next to one that placed it in idle mode. the interrupt latch (il) for the interrupt source used to exit idle mode normally needs to be cleared to 0 using a load instruction. b. released by interrupt (when imf = 1) the device can be released from idle mode by the interrupt source enabled by the interrupt individual enable flag (ef), and enters interrupt handling. after interrupt handling, the device returns to the instruction next to one that placed it in idle mode. the device can also be released from idle mode by pulling the reset pin input low, in which case the device is immediately reset as is normally reset by reset. after reset, the device starts operating from normal mode. note:if a watchdog timer interrupt occurs immediately before entering idle mode, the device pro- cesses the watchdog timer interrupt without entering idle mode. TMP88FW45AFG page 21 figure 2-11 entering and exiting idle mode TMP88FW45AFG 2. functional description 2.1 functions of the cpu core page 22 (b) exiting idle mode (a) entering idle mode (example: entered into by the set instruction placed at address a) idle a + 2 a + 3 set (syscr2). 4 operating 1. released normally idle idle a + 3 a + 4 instruction at address a + 2 operating 2. released by interrupt idle idle a + 3 interrupt accepted operating main system clock interrupt request program counter instruction execution main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer watchdog timer 2.1.5 reset circuit the TMP88FW45AFG has five ways to generate a reset: external reset input, address trap reset, watchdog timer reset , system clock reset and oscillation frequency detection reset. table 2-3 shows how the internal hardware is initialized by reset operation. at power-on time, the internal cause reset circuits (watchdog timer reset, address trap reset, and system clock reset) are not initialized. table 2-3 internal hardware initialization by reset operation internal hardware initial value internal hardware initial value program counter (pc) (ffffeh to ffffch) prescaler and divider for the timing generator 0 stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l) not initialized register bank selector (rbs) 0 watchdog timer enable jump status flag (jf) 1 zero flag (zf) not initialized output latch of input/output port see description of each input/output port. carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 interrupt individual enable flag (ef) 0 control register see description of each control register. interrupt latch (il) 0 interrupt nesting flag (inf) 0 ram not initialized 2.1.5.1 external reset input the reset pin is a hysteresis input with a pull-up resistor included. by holding the reset pin low for at least three machine cycles (12/fc [s]) or more while the power supply voltage is within the rated operating voltage range and the oscillator is oscillating stably, the device is reset and its internal state is initialized. when the reset pin input is released back high, the device is freed from reset and starts executing the program beginning with the vector address stored at addresses ffffch to ffffeh. figure 2-12 reset circuit 2.1.5.2 address trap reset if the cpu should start looping for reasons of noise, etc. and attempts to fetch instructions from the internal ram,sfr or dbr/ebr area, the device generates an internal reset. the address trap permission/prohibition is set by the address trap reset control register (atas,atkey). the address trap is permitted initially and the internal reset is generated by fetching from internal ram,sfr or dbr/ebr area. if the address trap is prohibited, instructions in the internal ram area can be executed. TMP88FW45AFG page 23 reset input vdd reset address trap control register atas (1f94h) 7 6 5 4 3 2 1 0 - - - - - - - atas (initial value: **** ***0) atas select the address trap permission / prohibition 0: permit address trap 1: prohibit address trap (it may be available after setting control code for atkey register) write only address trap control code register atkey (1f95h) 7 6 5 4 3 2 1 0 (initial value: **** ****) atkey write control code to prohibit address trap d2h: address trap prohibition code others: ineffective write only note:read-modify-write instructions, such as a bit manipulation, cannot access atas or atkey register because these register are write only. note 1: in development tools, address trap cannot be prohibited in the internal ram,sfr or dbr/ebr area with the address trap control registers. when using development tools, even if the address trap permission/ prohibition setting is changed in the users program, this change is ineffective. to execute instructions from the ram area, development tools must be set accordingly. note 2: while the swi instruction at an address immediately before the address trap area is executing, the program counter is incremented to point to the next address in the address trap area; an address trap is therefore taken immediately. development tool setting ? to prohibit the address trap: 1. modify the iram (mapping attribute) area to (00040h to 000bfh) in the memory map win- dow. 2. set 000c0h to "address trap prohibition area" as a new eram (mapping attribute) area. 3. load the user program 4. execute the address trap prohibition code in the users program 2.1.5.3 watchdog timer reset refer to the section watchdog timer. 2.1.5.4 system clock reset when syscr2 3. interrupt control circuit the TMP88FW45AFG has a total of 36 interrupt sources excluding reset. interrupts can be nested with priorities. two of the internal interrupt sources are pseudo non-maskable while the rest are maskable. interrupt sources are provided with interrupt latches (il), which hold interrupt requests, and independent vectors. the interrupt latch is set to 1 by the generation of its interrupt request which requests the cpu to accept its interrupts. interrupts are enabled or disabled by software using the interrupt master enable flag (imf) and interrupt enable flag (ef). if more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. however, there are no prioritized interrupt factors among non-maskable interrupts. interrupt factors enable condition interrupt latch vector ad- dress priority internal/external (reset) non-maskable - ffffc high 0 internal intswi (software interrupt) pseudo non-maskable - ffff8 1 internal intwdt (watchdog timer interrupt) pseudo non-maskable il2 ffff4 2 external int0 (external interrupt 0) imf? ef3 = 1, int0en = 1 il3 ffff0 3 reserved imf? ef4 = 1 il4 fffec 4 external int1 (external interrupt 1) imf? ef5 = 1 il5 fffe8 5 internal inttbt (tbt interrupt) imf? ef6 = 1 il6 fffe4 6 reserved imf? ef7 = 1 il7 fffe0 7 internal intemg1 (ch1 error detect interrupt) imf? ef8 = 1 il8 fffdc 8 internal intemg2 (ch2 error detect interrupt) imf? ef9 = 1 il9 fffd8 9 internal intclm1 (ch1 overload protection interrupt) imf? ef10 = 1 il10 fffd4 10 internal intclm2 (ch2 overload protection interrupt) imf? ef11 = 1 il11 fffd0 11 internal inttmr31 (ch1 timer 3 interrupt) imf? ef12 = 1 il12 fffcc 12 internal inttmr32 (ch2 timer 3 interrupt) imf? ef13 = 1 il13 fffc8 13 reserved imf? ef14 = 1 il14 fffc4 14 external int5 (external interrupt 5) imf? ef15 = 1 il15 fffc0 15 internal intpdc1 (ch1 position detect interrupt) imf? ef16 = 1 il16 fffbc 16 internal intpdc2 (ch2 position detect interrupt) imf? ef17 = 1 il17 fffb8 17 internal intpwm1 (ch1 waveform generates interrupt) imf? ef18 = 1 il18 fffb4 18 internal intpwm2 (ch2 waveform generates interrupt) imf? ef19 = 1 il19 fffb0 19 internal intedt1 (ch1 electric angle timer interrupt) imf? ef20 = 1 il20 fffac 20 internal intedt2 (ch2 electric angle timer interrupt) imf? ef21 = 1 il21 fffa8 21 internal inttmr11 (ch1 timer1 interrupt) imf? ef22 = 1 il22 fffa4 22 internal inttmr12 (ch2 timer1 interrupt) imf? ef23 = 1 il23 fffa0 23 internal inttmr21 (ch1 timer2 interrupt) imf? ef24 = 1 il24 fff9c 24 internal inttmr22 (ch2 timer2 interrupt) imf? ef25 = 1 il25 fff98 25 internal inttc1 (tc1 interrupt) imf? ef26 = 1 il26 fff94 26 internal intctc (ctc interrupt) imf? ef27 = 1 il27 fff90 27 internal inttc6 (tc6 8bit/16bit interrupt) imf? ef28 = 1 il28 fff8c 28 external int2 (external interrupt 2) imf? ef29 = 1 il29 fff88 29 internal intrxd2 (ch2 uart receive interrupt) imf? ef30 = 1 il30 fff84 30 external int4 (external interrupt 4) imf? ef31 = 1 il31 fff80 31 internal intrxd (ch1 uart receive interrupt) imf? ef32 = 1 il32 fff3c 32 internal inttxd (ch1 uart transmit interrupt) imf? ef33 = 1 il33 fff38 33 internal intsio (sio interrupt) imf? ef34 = 1 il34 fff34 34 internal inttc3 (tc3 interrupt) imf? ef35= 1 il35 fff30 35 internal inttc4 (tc4 interrupt) imf? ef36 = 1 il36 fff2c 36 internal inttc5 (tc5 interrupt) imf? ef37 = 1 il37 fff28 37 internal intadc (a/d converter interrupt) imf? ef38 = 1 il38 fff24 38 internal inttxd2 (ch2 uart transmit interrupt) imf? ef39 = 1 il39 fff20 low 39 TMP88FW45AFG page 25 note 1: to use the watchdog timer interrupt (intwdt), clear wdtcr1 3.2 interrupt enable register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except for the pseudo non- maskable interrupts (software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). pseudo non-maskable interrupt is accepted regardless of the contents of the eir. the eir consists of an interrupt master enable flag (imf) and the individual interrupt enable flags (ef). these registers are located on address 003ah, 003bh, 002ch, 002dh and 002ah in sfr area, and they can be read and written by an instructions (including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 interrupt master enable flag (imf) the interrupt enable register (imf) enables and disables the acceptance of the whole maskable interrupt. while imf = 0, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (ef). by setting imf to 1, the interrupt becomes acceptable if the individuals are enabled. when an interrupt is accepted, imf is cleared to 0 after the latest status on imf is stacked. thus the maskable interrupts which follow are disabled temporarily. imf flag is set to "1" by the maskable interrupt return instruction [reti] after executing the interrupt service program routine, and mcu can accept the interrupt again. the latest interrupt request is generated already, it is available immediately after the [reti] instruction is executed. on the pseudo non-maskable interrupt, the non-maskable return instruction [retn] is adopted. in this case, imf flag is set to "1" only when it performs the pseudo non-maskable interrupt service routine on the interrupt acceptable status (imf=1). however, imf is set to "0" in the pseudo non-maskable interrupt service routine, it maintains its status (imf="0"). the imf is located on bit0 in eirl (address: 003ah in sfr), and can be read and written by an instruction. the imf is normally set and cleared by [ei] and [di] instruction respectively. during reset, the imf is initialized to 0. 3.2.2 individual interrupt enable flags (ef39 to ef3) each of these flags enables and disables the acceptance of its maskable interrupt. setting the corresponding bit of an individual interrupt enable flag to 1 enables acceptance of its interrupt, and setting the bit to 0 disables acceptance. during reset, all the individual interrupt enable flags (ef39 to ef3) are initialized to 0 and all maskable interrupts are not accepted until they are set to 1. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple interrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". example :enables interrupts individually and sets imf di ; imf 0 set (eirl), .5 ; ef5 1 clr (eirl), .6 ; ef6 0 clr (eirh), .4 ; ef12 0 clr (eird), .0 ; ef24 0 : ei ; imf 1 TMP88FW45AFG page 27 interrupt latches (initial value: 0*000000 *00*0000) ilh,ill (003dh, 003ch) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 il15 - il13 il12 il11 il10 il9 il8 - il6 il5 - il3 il2 inf ilh (003dh) ill (003ch) (initial value: 00000000 00000000) ild,ile (002fh, 002eh) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 il31 il30 il29 il28 il27 il26 il25 il24 il23 il22 il21 il20 il19 il18 il17 il16 ild (002fh) ile (002eh) (initial value: 00000000) ilc (002bh) 7 6 5 4 3 2 1 0 il39 il38 il37 il36 il35 il34 il33 il32 ile (002bh) il39 to il2 interrupt latches read write r/w 0: no interrupt request 1: interrupt request 0: clears the interrupt request (note1) 1: (unable to set interrupt latch) inf interrupt nesting flag 00: out of interrupt service 01: on interrupt service of level 1 10: on interrupt service of more than level 2 11: on interrupt service of more than level 3 00: reserved 01: clear the nesting counter 10: count-down 1 step for the nesting counter (note2) 11: reserved note 1: il2 cannot alone be cleared. note 2: unable to detect the under-flow of counter. note 3: the nesting counter is set "0" initially, it performs count-up by the interrupt acceptance and count-down by executing the interrupt return instruction. note 4: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple interrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". note 5: do not clear il with read-modify-write instructions such as bit operations. TMP88FW45AFG 3. interrupt control circuit 3.2 interrupt enable register (eir) page 28 interrupt enable registers (initial value: 0*000000 *00*0**0) eirh,eirl (003bh, 003ah) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ef15 - ef13 ef12 ef11 ef10 ef9 ef8 - ef6 ef5 - ef3 imf eirh (003bh) eirl (003ah) (initial value: 00000000 00000000) eird,eire (002dh, 002ch) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ef31 ef30 ef29 ef28 ef27 ef26 ef25 ef24 ef23 ef22 ef21 ef20 ef19 ef18 ef17 ef16 eird (002dh) eire (002ch) (initial value: 00000000) eire (002ah) 7 6 5 4 3 2 1 0 ef39 ef38 ef37 ef36 ef35 ef34 ef33 ef32 eire (002ah) ef39 to ef3 individual-interrupt enable flag (specified for each bit) 0: 1: disables the acceptance of each maskable interrupt. enables the acceptance of each maskable interrupt. r/w imf interrupt master enable flag 0: 1: disables the acceptance of all maskable interrupts enables the acceptance of all maskable interrupts note 1: do not set imf and the interrupt enable flag (ef39 to ef3) to 1 at the same time. note 2: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple interrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". TMP88FW45AFG page 29 3.3 interrupt sequence an interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to 0 by resetting or an instruction. interrupt acceptance sequence requires 12 machine cycles (2.4 s @20 mhz) after the completion of the current instruction. the interrupt service task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for non-maskable interrupts). figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 interrupt acceptance processing is packaged as follows. a. the interrupt master enable flag (imf) is cleared to 0 in order to disable the acceptance of any following interrupt. b. the interrupt latch (il) for the interrupt source accepted is cleared to 0. c. the contents of the program counter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the stack in sequence of pswh, pswl, pce, pch, pcl. meanwhile, the stack pointer (sp) is decremented by 5. d. the entry address (interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. e. read the rbs control code from the vector table, add its msb(4bit) to the register bank selector (rbs). f. count up the interrupt nesting counter. g. the instruction stored at the entry address of the interrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of imf are also saved. note 1: a: return address, b: entry address, c: address which reti instruction is stored note 2: on condition that interrupt is enabled, it takes 62/fc [s] at maximum (if the interrupt latch is set at the first machine cycle on 15 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. figure 3-1 timing chart of interrupt acceptance/return interrupt instruction example: correspondence between vector table address for inttbt and the entry address of the interrupt service program TMP88FW45AFG 3. interrupt control circuit 3.3 interrupt sequence page 30 interrupt request interrupt latch (il) imf execute instruction pc sp 1-machine cycle interrupt service task n-3 n-4 n-4 a n-3 n n-5 a-1 a b b+1 b+2 a+1 a+2 b+3 c+2 c+1 execute instruction execute instruction execute reti instruction interrupt acceptance a+1 a n n-2 n-1 n-2 n-1 figure 3-2 vector table address, entry address a maskable interrupt is not accepted until the imf is set to 1 even if the maskable interrupt higher than the level of current servicing interrupt is requested. in order to utilize nested interrupt service, the imf is set to 1 in the interrupt service program. in this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. but dont use the read-modify-write instruction for eirl(0003ah) on the pseudo non-maskable interrupt service task. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to 1. as for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.3.2 saving/restoring general-purpose registers during interrupt acceptance processing, the program counter (pc) and the program status word (psw, includes imf) are automatically saved on the stack, but the accumulator and others are not. these registers are saved by software if necessary. when multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. the following four methods are used to save/restore the general-purpose registers. 3.3.2.1 using automatic register bank switching by switching to non-use register bank, it can restore the general-purpose register at high speed. usually the bank register "0" is assigned for main task and the bank register "1 to 15" are for the each interrupt service task. to make up its data memory efficiency, the common bank is assigned for non-multiple interrupt factor. it can return back to main-flow by executing the interrupt return instructions ([reti]/[retn]) from the current interrupt register bank automatically. thus, no need to restore the rbs by a program. example :register bank switching pintxx: (interrupt processing) ; begin of interrupt routine reti ; end of interrupt : vintxx: dp pintxx ; pintxx vector address setting db 1 ; rbs <- rbs + 1 rbs setting on pintxx 3.3.2.2 using register bank switching by switching to non-use register bank, it can restore the general-purpose register at high speed. usually the bank register "0" is assigned for main task and the bank register "1 to 15" are for the each interrupt service task. TMP88FW45AFG page 31 45h 23h 01h 06h fffe4h fffe5h fffe6h fffe7h vector rbs control code vector table address 12345h 12346h 12347h 12348h entry address interrupt service program example :register bank switching pintxx: ld rbs, n ; rbs <- n begin of interrupt routine (interrupt processing) reti ; end of interrupt, restore rbs and interrupt return : vintxx: dp pintxx ; pintxx vector address setting db 0 ; rbs <- rbs + 0 rbs setting on pintxx 3.3.2.3 using push and pop instructions if only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the push/pop instructions. example :save/store register using push and pop instructions pintxx: push wa ; save wa register (interrupt processing) pop wa ; restore wa register reti ; return figure 3-3 save/store register using push and pop instructions 3.3.2.4 using data transfer instructions to save only a specific register without nested interrupts, data transfer instructions are available. example :save/store register using data transfer instructions pintxx: ld (gsava), a ; save a register (interrupt processing) ld a, (gsava) ; restore a register reti ; return TMP88FW45AFG 3. interrupt control circuit 3.3 interrupt sequence page 32 pc l pc h psw l psw h at acceptance of an interrupt pc l pc h psw l psw h a w pc l pc h psw l psw h b-5 b-4 b-3 b-2 b-1 b address (example) sp sp sp sp at execution of push instruction at execution of pop instruction at execution of reti instruction figure 3-4 saving/restoring general-purpose registers under interrupt processing 3.3.3 interrupt return interrupt return instructions [reti]/[retn] perform as follows. [reti] maskable interrupt return [retn] non-maskable interrupt return 1. the contents of the program counter and the program status word are restored from the stack. 2. the stack pointer is incremented 5 times. 3. the interrupt master enable flag is set to "1". 4. the interrupt nesting counter is decremented, and the interrupt nesting flag is changed. 1. the contents of the program counter and the program status word are restored from the stack. 2. the stack pointer is incremented 5 times. 3. the interrupt master enable flag is set to "1" only when a non-maskable interrupt is accepted in interrupt enable status. however, the interrupt master enable flag remains at "0" when so clear by an interrupt service program. 4. the interrupt nesting counter is decremented, and the interrupt nesting flag is changed. interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. note:when the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. TMP88FW45AFG page 33 main task interrupt acceptance interrupt return interrupt service task saving registers restoring registers main task bank m interrupt acceptance interrupt return interrupt service task switch to bank n automatically restore to bank m automatically by [reti]/[retn] bank m bank n switch to bank n by ld, rbs and n instruction (a) saving/restoring by register bank changeover (b) saving/restoring general-purpose registers using push/pop data transfer instruction bank m 3.4 software interrupt (intsw) executing the swi instruction generates a software interrupt and immediately starts interrupt processing (intsw is highest prioritized interrupt). however, if processing of a non-maskable interrupt is already underway, executing the swi instruction will not generate a software interrupt but will result in the same operation as the nop instruction. use the swi instruction only for detection of the address error or for debugging. 3.4.1 address error detection ffh is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address during single chip mode. code ffh is the swi instruction, so a software interrupt is generated and an address error is detected. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address trap reset is generated in case that an instruction is fetched from ram, dbr or sfr areas. 3.4.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. TMP88FW45AFG 3. interrupt control circuit 3.4 software interrupt (intsw) page 34 3.5 external interrupts the TMP88FW45AFG has 5 external interrupt inputs. these inputs are equipped with digital noise reject circuits (pulse inputs of less than a certain time are eliminated as noise). edge selection is also possible with int1,int2 and int4. the int0/p10 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. edge selection, and noise reject control and int0/p10 pin function selection are performed by the external interrupt control register (eintcr). source pin sub-pin enable conditions release edge (level) digital noise reject int0 int0 p10 imf + ef3 + int0en=1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 6/fc [s] or more are considered to be signals. (at cgcr TMP88FW45AFG 3. interrupt control circuit 3.5 external interrupts page 36 4. special function register the TMP88FW45AFG adopts the memory mapped i/o system, and all peripheral control and transfers are per- formed through the special function register (sfr) or the data buffer register (dbr,ebr). the sfr is mapped on address 0000h to 003fh, dbr is mappped on address 1f80h to 1fffh and ebr is mappped on address 1f70h to 1f7fh. this chapter shows the arrangement of the special function register (sfr) and data buffer register (dbr,ebr) for TMP88FW45AFG. 4.1 sfr address read write 0000h p0dr 0001h p1dr 0002h p2dr 0003h p3dr 0004h p4dr 0005h p5dr 0006h p6dr 0007h p7dr 0008h p8dr 0009h p9dr 000ah p0cr 000bh p1cr 000ch hpwmcr 000dh hpwmdr0 000eh hpwmdr1 000fh tc1cr 0010h tc1dral 0011h tc1drah 0012h tc1drbl 0013h tc1drbh 0014h ctc1cr1 0015h ctc1cr2 0016h - ctc1drl 0017h - ctc1drh 0018h reserved 0019h reserved 001ah tc4cr 001bh tc4dr 001ch tc3dra 001dh tc3drb - 001eh tc3cr 001fh reserved 0020h tc5cr 0021h tc6cr 0022h ttreg5 0023h ttreg6 0024h pwreg5 TMP88FW45AFG page 37 address read write 0025h pwreg6 0026h adccra 0027h adccrb 0028h adcdrl - 0029h adcdrh - 002ah eirc 002bh ilc 002ch eire 002dh eird 002eh ile 002fh ild 0030h cgcr 0031h reserved 0032h reserved 0033h reserved 0034h - wdtcr1 0035h - wdtcr2 0036h tbtcr 0037h eintcr 0038h syscr1 0039h syscr2 003ah eirl 003bh eirh 003ch ill 003dh ilh 003eh pswl 003fh pswh note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). TMP88FW45AFG 4. special function register 4.1 sfr page 38 4.2 ebr address read write 1f70h uartsr2 uartcr21 1f71h ? uartcr22 1f72h rdbuf2 tdbuf2 1f73h reserved 1f74h reserved 1f75h reserved 1f76h reserved 1f77h reserved 1f78h reserved 1f79h reserved 1f7ah reserved 1f7bh reserved 1f7ch clkscr2 1f7dh clksmn 1f7eh clksmx 1f7fh clkscr1 note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). TMP88FW45AFG page 39 4.3 dbr address pmd ch read write 1f80h p0ode 1f81h ? 1f82h ? 1f83h p3ode 1f84h p4ode 1f85h p5ode 1f86h p8ode 1f87h p9ode 1f88h ? 1f89h p3cr 1f8ah p4cr 1f8bh p5cr 1f8ch p6cr 1f8dh p7cr 1f8eh p8cr 1f8fh p9cr 1f90h uartsel 1f91h uartsr uartcr1 1f92h ? uartcr2 1f93h rdbuf tdbuf 1f94h ? atas 1f95h ? atkey 1f96h ? siocr1 1f97h siosr siocr2 1f98h siobr0 1f99h siobr1 1f9ah siobr2 1f9bh siobr3 1f9ch siobr4 1f9dh siobr5 1f9eh siobr6 1f9fh siobr7 1fa0h for pmd ch.1 pdcra 1fa1h for pmd ch.1 pdcrb 1fa2h for pmd ch.1 pdcrc ? 1fa3h for pmd ch.1 sdreg 1fa4h for pmd ch.1 mtcra 1fa5h for pmd ch.1 mtcrb 1fa6h for pmd ch.1 mcapl ? 1fa7h for pmd ch.1 mcaph ? 1fa8h for pmd ch.1 cmp1l 1fa9h for pmd ch.1 cmp1h 1faah for pmd ch.1 cmp2l 1fabh for pmd ch.1 cmp2h 1fach for pmd ch.1 cmp3l 1fadh for pmd ch.1 cmp3h 1faeh for pmd ch.1 mdcra 1fafh for pmd ch.1 mdcrb TMP88FW45AFG 4. special function register 4.3 dbr page 40 address pmd ch read write 1fb0h for pmd ch.1 emgcra 1fb1h for pmd ch.1 emgcrb 1fb2h for pmd ch.1 mdoutl 1fb3h for pmd ch.1 mdouth 1fb4h for pmd ch.1 mdcntl ? 1fb5h for pmd ch.1 mdcnth ? 1fb6h for pmd ch.1 mdprdl 1fb7h for pmd ch.1 mdprdh 1fb8h for pmd ch.1 cmpul 1fb9h for pmd ch.1 cmpuh 1fbah for pmd ch.1 cmpvl 1fbbh for pmd ch.1 cmpvh 1fbch for pmd ch.1 cmpwl 1fbdh for pmd ch.1 cmpwh 1fbeh for pmd ch.1 dtr 1fbfh for pmd ch.1 ? emgrel 1fc0h for pmd ch.1 edcra 1fc1h for pmd ch.1 edcrb 1fc2h for pmd ch.1 edsetl 1fc3h for pmd ch.1 edseth 1fc4h for pmd ch.1 eldegl 1fc5h for pmd ch.1 eldegh 1fc6h for pmd ch.1 ampl 1fc7h for pmd ch.1 amph 1fc8h for pmd ch.1 edcapl ? 1fc9h for pmd ch.1 edcaph ? 1fcah for pmd ch.1 ? wfmdr 1fcbh ? 1fcch reserved 1fcdh reserved 1fceh reserved 1fcfh reserved 1fd0h for pmd ch.2 pdcra 1fd1h for pmd ch.2 pdcrb 1fd2h for pmd ch.2 pdcrc ? 1fd3h for pmd ch.2 sdreg 1fd4h for pmd ch.2 mtcra 1fd5h for pmd ch.2 mtcrb 1fd6h for pmd ch.2 mcapl ? 1fd7h for pmd ch.2 mcaph ? 1fd8h for pmd ch.2 cmp1l 1fd9h for pmd ch.2 cmp1h 1fdah for pmd ch.2 cmp2l 1fdbh for pmd ch.2 cmp2h 1fdch for pmd ch.2 cmp3l 1fddh for pmd ch.2 cmp3h 1fdeh for pmd ch.2 mdcra 1fdfh for pmd ch.2 mdcrb 1fe0h for pmd ch.2 emgcra TMP88FW45AFG page 41 address pmd ch read write 1fe1h for pmd ch.2 emgcrb 1fe2h for pmd ch.2 mdoutl 1fe3h for pmd ch.2 mdouth 1fe4h for pmd ch.2 mdcntl ? 1fe5h for pmd ch.2 mdcnth ? 1fe6h for pmd ch.2 mdprdl 1fe7h for pmd ch.2 mdprdh 1fe8h for pmd ch.2 cmpul 1fe9h for pmd ch.2 cmpuh 1feah for pmd ch.2 cmpvl 1febh for pmd ch.2 cmpvh 1fech for pmd ch.2 cmpwl 1fedh for pmd ch.2 cmpwh 1feeh for pmd ch.2 dtr 1fefh for pmd ch.2 ? emgrel 1ff0h for pmd ch.2 edcra 1ff1h for pmd ch.2 edcrb 1ff2h for pmd ch.2 edsetl 1ff3h for pmd ch.2 edseth 1ff4h for pmd ch.2 eldegl 1ff5h for pmd ch.2 eldegh 1ff6h for pmd ch.2 ampl 1ff7h for pmd ch.2 amph 1ff8h for pmd ch.2 edcapl ? 1ff9h for pmd ch.2 edcaph ? 1ffah for pmd ch.2 ? wfmdr 1ffbh ? 1ffch reserved 1ffdh reserved 1ffeh spcr 1fffh flscr note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). TMP88FW45AFG 4. special function register 4.3 dbr page 42 5. input/output ports the TMP88FW45AFG contains 10 input/output ports comprised of 71 pins. primary function secondary functions port p0 4-bit i/o port timer/counter input, serial interface input/output, and high-speed pwm out- put port p1 8-bit i/o port external interrupt input, timer/counter input/output, divider output, and motor control circuit input port p2 3-bit i/o port external interrupt input, timer/counter input/output, and stop mode release signal input port p3 8-bit i/o port motor control input/output port p4 8-bit i/o port timer/counter output, serial interface input/output, motor control circuit input and serial prom mode control input port p5 8-bit i/o port motor control circuit input/output port p6 8-bit i/o port analog input and motor control circuit output port p7 8-bit i/o port analog input and motor control circuit output port p8 8-bit i/o port serial interface input/output port p9 8-bit i/o port all output ports contain a latch, and the output data therefore are retained by the latch. but none of the input ports have a latch, so it is desirable that the input data be retained externally until it is read out, or read several times before being processed. figure 5-1 shows input/output timing. the timing at which external data is read in from input/output ports is s1 state in the read cycle of instruction execution. because this timing cannot be recognized from the outside, transient input data such as chattering needs to be dealt with in a program. the timing at which data is forwarded to input/output ports is s2 state in the write cycle of instruction execution. if high frequency oscillation stops or becomes abnormal in normal/idle mode, the TMP88FW45AFG generates the oscillation frequency detection reset and all i/o pins become high impedance. note:the read/write cycle positions vary depending on instructions. figure 5-1 example of input/output timing TMP88FW45AFG page 43 ! "! #! $! ! "! #! $! ! "! #! $ % & ! "! #! $! ! "! #! $! ! "! #! $ ' % ' when an operation is performed for read from any input/output port except programmable input/output ports, whether the input value of the pin or the content of the output latch is read depends on the instruction executed, as shown below. 1. instructions which read the content of the output latch - xch r, (src) - set/clr/cpl (src).b - set/clr/cpl (pp).g - ld (src).b, cf - ld (pp).b, cf - xch cf, (src). b - add/addc/sub/subb/and/or/xor (src), n - add/addc/sub/subb/and/or/xor (src), (hl) instructions, the (src) side thereof - mxor (src), m 2. instructions which read the input value of the pin any instructions other than those listed above and add/addc/sub/subb/and/or/xor (src),(hl) instructions, the (hl) side thereof TMP88FW45AFG 5. input/output ports page 44 5.1 port p0 (p03 to p00) port p0 is a 4-bit input/output port shared with serial interface input/output. this port is switched between input and output modes using the p0 port input/output control register (p0cr). when reset, the p0cr register is initialized to 0, with the p0 port set for input mode. also, the output latch (p0dr) is initialized to 0 when reset. the p0 port contains bit wise programmable open-drain control. the p0 port open-drain control register (p0ode) is used to select open-drain or tri-state mode for the port. when reset, the p0ode register is initialized to 0, with tri- state mode selected for the port. if high frequency oscillation stops or becomes abnormal in normal/idle mode, the TMP88FW45AFG generates the oscillation frequency detection reset and port p0 becomes high impedance. table 5-1 p0ode p0cr p0dr data input (by reading instruction) control input output data 0 0 0 input data from port input data from port hi-z 0 0 1 input data from port input data from port hi-z 0 1 0 "0" (output latch data) "0" (output latch data) "0" 0 1 1 "1" (output latch data) "1" (output latch data) "1" 1 0 0 input data from port (low) input data from port (low) "0" 1 0 1 input data from port input data from port hi-z 1 1 0 input data from port (low) input data from port (low) "0" 1 1 1 input data from port input data from port hi-z note 1: i = 3 to 0 note 2: ofdrst shows a reset signal of oscillation frequency detection. figure 5-2 port p0 TMP88FW45AFG page 45 output latch p0cri data output control input control output data input p0i stop outen ofdrst p0odei d q p0 port input/output registers p0dr (00000h) 7 6 5 4 3 2 1 0 p03 hpwm1 p02 hpwm0 p01 tc6o txd2 p00 tc6i rxd2 read/write (initial value: **** 0000) p0cr (0000ah) 7 6 5 4 3 2 1 0 (initial value: **** 0000) p0cr p0 port input/output control (specify bit wise) 0: input mode 1: output mode r/w p0ode (01f80h) 7 6 5 4 3 2 1 0 (initial value: **** 0000) p0ode p0 port open-drain control (specify bit wise) 0: tri-state 1: open-drain r/w note 1: even when open-drain mode is selected, the protective diode remains connected. therefore, do not apply voltages ex- ceeding v dd . note 2: read-modify-write (rmw) operation executes at open-drain mode is selected, read out the output latch states. when any other instruction is executed, external pin states is read out. note 3: *: dont care note 4: tc6o: pdo6, pwm6, ppg6 TMP88FW45AFG 5. input/output ports 5.1 port p0 (p03 to p00) page 46 5.2 port p1 (p17 to p10) port p1 is an 8-bit input/output port shared with external interrupt input, timer/counter input/output, and divider output. this port is switched between input and output modes using the p1 port input/output control register (p1cr). when reset, the p1cr register is initialized to 0, with the p1 port set for input mode. also, the output latch (p1dr) is initialized to 0 when reset. if high frequency oscillation stops or becomes abnormal in normal/idle mode, the TMP88FW45AFG generates the oscillation frequency detection reset and port p1 becomes high impedance. table 5-2 p1ode p1cr p1dr data input (by reading instruction) control input output data 0 0 0 input data from port input data from port hi-z 0 0 1 input data from port input data from port hi-z 0 1 0 "0" (output latch data) "0" (output latch data) "0" 0 1 1 "1" (output latch data) "1" (output latch data) "1" 1 0 0 input data from port (low) input data from port (low) "0" 1 0 1 input data from port input data from port hi-z 1 1 0 input data from port (low) input data from port (low) "0" 1 1 1 input data from port input data from port hi-z note 1: i = 7 to 0 note 2: ofdrst shows a reset signal of oscillation frequency detection. figure 5-3 port p1 p1 port input/output registers p1dr (00001h) 7 6 5 4 3 2 1 0 p17 pdw2 p16 pdv2 p15 pdu2 p14 ppg1 tc5o p13 dvo tc5i p12 int2 tc1 p11 int1 p10 int0 read/write (initial value: 0000 0000) tc5o: pdo5, pwm5 p1cr (0000bh) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p1cr p1 port input/output control (specify bit wise) 0: input mode 1: output mode r/w note 1: tc5o: pdo5, pwm5 TMP88FW45AFG page 47 output latch p1cri data output control input control output data input p1i stop outen ofdrst p1odei d q 5.3 port p2 (p22 to p20) port p2 is a 3-bit input/output port shared with external interrupt input and stop mode release signal. when using this port as these functional pins or an input port, set the output latch to 1. when reset, the output latch is initialized to 1. we recommend using the p20 pin as external interrupt input, stop mode release signal input, or input port. when using this port as an output port, note that the interrupt latch is set by a falling edge of output pulse. and note that outputs on this port during stop mode go to a high-impedance state even if syscr1 note 2: port p20 is used as stop pin. therefore, when stop mode is started, syscr1 5.4 port p3 (p37 to p30) port p3 is an 8-bit input/output port. this port is switched between input and output modes using the p3 port input/ output control register (p3cr). when reset, the p3cr register is initialized to 0, with the p3 port set for input mode. also, the output latch (p3dr) is initialized to 0 when reset. the p3 port contains bit wise programmable open-drain control. the p3 port open-drain control register (p3ode) is used to select open-drain or tri-state mode for the port. when reset, the p3ode register is initialized to 0, with tri- state mode selected for the port. if high frequency oscillation stops or becomes abnormal in normal/idle mode, the TMP88FW45AFG generates the oscillation frequency detection reset and port p3 becomes high impedance. table 5-3 p3ode p3cr p3dr data input (by reading instruction) control input output data 0 0 0 input data from port input data from port hi-z 0 0 1 input data from port input data from port hi-z 0 1 0 "0" (output latch data) "0" (output latch data) "0" 0 1 1 "1" (output latch data) "1" (output latch data) "1" 1 0 0 input data from port (low) input data from port (low) "0" 1 0 1 input data from port input data from port hi-z 1 1 0 input data from port (low) input data from port (low) "0" 1 1 1 input data from port input data from port hi-z note 1: i = 7 to 0 note 2: ofdrst shows a reset signal of oscillation frequency detection. figure 5-5 port p3 TMP88FW45AFG 5. input/output ports 5.4 port p3 (p37 to p30) page 50 output latch p3cri data output control input control output data input p3i stop outen ofdrst p3odei d q p3 port input/output registers p3dr (00003h) 7 6 5 4 3 2 1 0 p37 cl1 p36 emg1 p35 u1 p34 v1 p33 w1 p32 x1 p31 y1 p30 z1 read/write (initial value: 0000 0000) p3cr (01f89h) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p3cr p3 port input/output control (specify bit wise) 0: input mode 1: output mode r/w p3ode (01f83h) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p3ode p3 port open-drain control (specify bit wise) 0: tri-state 1: open-drain r/w note 1: even when open-drain mode is selected, the protective diode remains connected. therefore, do not apply voltages ex- ceeding v dd . note 2: read-modify-write (rmw) operation executes at open-drain mode is selected, read out the output latch states. when any other instruction is executed, external pin states is read out. note 3: for pmd circuit output, set the p3dr output latch to 1. note 4: when using p3 port as an input/output port, disable the emg1 circuit. TMP88FW45AFG page 51 5.5 port p4 (p47 to p40) port p4 is an 8-bit input/output port shared with serial interface input/output and serial prom mode control input. this port is switched between input and output modes using the p4 port input/output control register (p4cr). when reset, the p4cr register is initialized to 0, with the p4 port set for input mode. also, the output latch (p4dr) is initialized to 0 when reset. the p4 port contains bit wise programmable open-drain control. the p4 port open-drain control register (p4ode) is used to select open-drain or tri-state mode for the port. when reset, the p4ode register is initialized to 0, with tri- state mode selected for the port. if high frequency oscillation stops or becomes abnormal in normal/idle mode, the TMP88FW45AFG generates the oscillation frequency detection reset and port p4 becomes high impedance. table 5-4 p4ode p4cr p4dr data input (by reading instruction) control input output data 0 0 0 input data from port input data from port hi-z 0 0 1 input data from port input data from port hi-z 0 1 0 "0" (output latch data) "0" (output latch data) "0" 0 1 1 "1" (output latch data) "1" (output latch data) "1" 1 0 0 input data from port (low) input data from port (low) "0" 1 0 1 input data from port input data from port hi-z 1 1 0 input data from port (low) input data from port (low) "0" 1 1 1 input data from port input data from port hi-z note 1: i = 7 to 0 note 2: ofdrst shows a reset signal of oscillation frequency detection. figure 5-6 port p4 TMP88FW45AFG 5. input/output ports 5.5 port p4 (p47 to p40) page 52 output latch p4cri data output control input control output data input p4i stop outen ofdrst p4odei d q p4 port input/output registers p4dr (00004h) 7 6 5 4 3 2 1 0 p47 ctc p46 ppg2 p45 so txd1 p44 si rxd1 boot p43 sck p42 pdu1 p41 pdv1 p40 pdw1 (initial value: 0000 0000) p4cr (01f8ah) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p4cr p4 port input/output control (specify bit wise) 0: input mode 1: output mode r/w p4ode (01f84h) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p4ode p4 port open-drain control (specify bit wise) 0: tri-state 1: open-drain r/w note 1: even when open-drain mode is selected, the protective diode remains connected. therefore, do not apply voltages ex- ceeding v dd . note 2: read-modify-write (rmw) operation executes at open-drain mode is selected, read out the output latch states. when any other instruction is executed, external pin states is read out. note 3: when using the 16-bit timer (ctc) as an ordinary timer, set p47 (ctc) for output mode. TMP88FW45AFG page 53 5.6 port p5 (p57 to p50) port p5 is an 8-bit input/output port. this port is switched between input and output modes using the p5 port input/ output control register (p5cr). when reset, the p5cr register is initialized to 0, with the p5 port set for input mode. also, the output latch (p5dr) is initialized to 0 when reset. the p5 port contains bit wise programmable open-drain control. the p5 port open-drain control register (p5ode) is used to select open-drain or tri-state mode for the port. when reset, the p5ode register is initialized to 0, with tri- state mode selected for the port. if high frequency oscillation stops or becomes abnormal in normal/idle mode, the TMP88FW45AFG generates the oscillation frequency detection reset and port p5 becomes high impedance. table 5-5 p5ode p5cr p5dr data input (by reading instruction) control input output data 0 0 0 input data from port input data from port hi-z 0 0 1 input data from port input data from port hi-z 0 1 0 "0" (output latch data) "0" (output latch data) "0" 0 1 1 "1" (output latch data) "1" (output latch data) "1" 1 0 0 input data from port (low) input data from port (low) "0" 1 0 1 input data from port input data from port hi-z 1 1 0 input data from port (low) input data from port (low) "0" 1 1 1 input data from port input data from port hi-z note 1: i = 7 to 0 note 2: ofdrst shows a reset signal of oscillation frequency detection. figure 5-7 port p5 p5 port input/output registers p5dr (00005h) 7 6 5 4 3 2 1 0 p57 z2 p56 y2 p55 x2 p54 w2 p53 v2 p52 u2 p51 emg2 p50 cl2 read/write (initial value: 0000 0000) p5cr (01f8bh) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p5cr p5 port input/output control (specify bit wise) 0: input mode 1: output mode r/w TMP88FW45AFG 5. input/output ports 5.6 port p5 (p57 to p50) page 54 output latch p5cri data output control input control output data input p5i stop outen ofdrst p5odei d q p5ode (01f85h) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p5ode p5 port open-drain control (specify bit wise) 0: tri-state 1: open-drain r/w note 1: even when open-drain mode is selected, the protective diode remains connected. therefore, do not apply voltages ex- ceeding v dd . note 2: read-modify-write (rmw) operation executes at open-drain mode is selected, read out the output latch states. when any other instruction is executed, external pin states is read out. note 3: for pmd circuit output, set the p5dr output latch to 1. note 4: when using p5 port as an input/output port, disable the emg2 circuit. TMP88FW45AFG page 55 5.7 port p6 (p67 to p60) port p6 is an 8-bit input/output port shared with ad converter analog input. this port is switched between input and output modes using the p6 port input/output control register (p6cr), p6 port output latch (p6dr), and adc- cra p6 port input/output registers p6dr (00006h) 7 6 5 4 3 2 1 0 p67 ain7 dbout1 p66 ain6 p65 ain5 p64 ain4 p63 ain3 p62 ain2 p61 ain1 p60 ain0 read/write (initial value: 0000 0000) p6cr (01f8ch) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p6cr p6 port input/output control (specify bit wise) ainds = 1 (when not using ad) ainds = 0 (when using ad) r/w p6dr = 0 p6dr = 1 p6dr = 0 p6dr = 1 0 inputs fixed to 0 input mode analog input mode (note2) input mode 1 output mode note 1: the pins used for analog input cannot be set for output mode (p6cr = 1) because they become shorted with external signals. note 2: when a read instruction is executed on bits of this port which are set for analog input mode, data "0" is read in. note 3: for dbout1 output, set the p6dr (p67) output latch to 1. note 4: when using this port in input mode (including analog input), do not use bit manipulating or other read-modify-write in- structions. when a read instruction is executed on the bits of this port that are set for input, the contents of the pins are read in, so that if a read-modify-write instruction is executed, their output latches may be rewritten, making the pins unable to accept input. (a read-modify-write instruction first reads data from all of the eight bits and after modifying them (bit manipulation), writes data for all of the eight bits to the output latches.) TMP88FW45AFG page 57 5.8 port p7 (p77 to p70) port p7 is an 8-bit input/output port shared with ad converter analog input. this port is switched between input and output modes using the p7 port input/output control register (p7cr), p7 port output latch (p7dr), and adc- cra p7 port input/output registers p7dr (00007h) 7 6 5 4 3 2 1 0 p77 ain15 dbout2 p76 ain14 p75 ain13 p74 ain12 p73 ain11 p72 ain10 p71 ain9 p70 ain8 read/write (initial value: 0000 0000) p7cr (01f8dh) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p7cr p7 port input/output control (specify bit wise) ainds = 1 (when not using ad) ainds = 0 (when using ad) r/w p7dr = 0 p7dr = 1 p7dr = 0 p7dr = 1 0 inputs fixed to 0 input mode analog input mode (note2) input mode 1 output mode note 1: the pins used for analog input cannot be set for output mode (p7cr = 1) because they become shorted with external signals. note 2: when a read instruction is executed on bits of this port which are set for analog input mode, data "0" is read in. note 3: for dbout2 output, set the p7dr (p77) output latch to 1. note 4: when using this port in input mode (including analog input), do not use bit manipulating or other read-modify-write in- structions. when a read instruction is executed on the bits of this port that are set for input, the contents of the pins are read in, so that if a read-modify-write instruction is executed, their output latches may be rewritten, making the pins unable to accept input. (a read-modify-write instruction first reads data from all of the eight bits and after modifying them (bit manipulation), writes data for all of the 8 bits to the output latches.) TMP88FW45AFG page 59 5.9 port p8 (p87 to p80) port p8 is an 8-bit input/output port. this port is switched between input and output modes using the p8 port input/ output control register (p8cr). when reset, the p8cr register is initialized to 0, with the p8 port set for input mode. also, the output latch (p8dr) is initialized to 0 when reset. the p8 port contains bit wise programmable open-drain control. the p8 port open-drain control register (p8ode) is used to select open-drain or tri-state mode for the port. when reset, the p8ode register is initialized to 0, with tri- state mode selected for the port. if high frequency oscillation stops or becomes abnormal in normal/idle mode, the TMP88FW45AFG generates the oscillation frequency detection reset and port p8 becomes high impedance. table 5-6 p8ode p8cr p8dr data input (by reading instruction) control input output data 0 0 0 input data from port input data from port hi-z 0 0 1 input data from port input data from port hi-z 0 1 0 "0" (output latch data) "0" (output latch data) "0" 0 1 1 "1" (output latch data) "1" (output latch data) "1" 1 0 0 input data from port (low) input data from port (low) "0" 1 0 1 input data from port input data from port hi-z 1 1 0 input data from port (low) input data from port (low) "0" 1 1 1 input data from port input data from port hi-z note 1: i = 7 to 2 note 2: j = 1, 0 note 3: ofdrst shows a reset signal of oscillation frequency detection. figure 5-10 port p8 TMP88FW45AFG 5. input/output ports 5.9 port p8 (p87 to p80) page 60 output latch p8crj data output control input control output data input p8j stop outen ofdrst p8odej d q output latch p8cri data output data input p8i stop outen ofdrst p8odei d q p8 port input/output registers p8dr (00008h) 7 6 5 4 3 2 1 0 p87 p86 p85 p84 p83 p82 p81 txd3 p80 rxd3 read/write (initial value: 0000 0000) p8cr (01f8eh) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p8cr p8 port input/output control (specify bit wise) 0: input mode 1: output mode r/w p8ode (01f86h) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p8ode p8 port open-drain control (specify bit wise) 0: tri-state 1: open-drain r/w note 1: even when open-drain mode is selected, the protective diode remains connected. therefore, do not apply voltages ex- ceeding v dd . note 2: read-modify-write (rmw) operation executes at open-drain mode is selected, read out the output latch states. when any other instruction is executed, external pin states is read out. TMP88FW45AFG page 61 5.10 port p9 (p97 to p90) port p9 is an 8-bit input/output port. this port is switched between input and output modes using the p9 port input/ output control register (p9cr). when reset, the p9cr register is initialized to 0, with the p9 port set for input mode. also, the output latch (p9dr) is initialized to 0 when reset. the p9 port contains bit wise programmable open-drain control. the p9 port open-drain control register (p9ode) is used to select open-drain or tri-state mode for the port. when reset, the p9ode register is initialized to 0, with tri- state mode selected for the port. if high frequency oscillation stops or becomes abnormal in normal/idle mode, the TMP88FW45AFG generates the oscillation frequency detection reset and port p9 becomes high impedance. table 5-7 p9ode p9cr p9dr data input (by reading instruction) control input output data 0 0 0 input data from port input data from port hi-z 0 0 1 input data from port input data from port hi-z 0 1 0 "0" (output latch data) "0" (output latch data) "0" 0 1 1 "1" (output latch data) "1" (output latch data) "1" 1 0 0 input data from port (low) input data from port (low) "0" 1 0 1 input data from port input data from port hi-z 1 1 0 input data from port (low) input data from port (low) "0" 1 1 1 input data from port input data from port hi-z note 1: i = 7 to 0 note 2: ofdrst shows a reset signal of oscillation frequency detection. figure 5-11 port p9 TMP88FW45AFG 5. input/output ports 5.10 port p9 (p97 to p90) page 62 output latch p9cri data output data input p9i stop outen ofdrst p9odei d q p9 port input/output registers p9dr (00009h) 7 6 5 4 3 2 1 0 p97 p96 p95 p94 p93 p92 p91 p90 read/write (initial value: 0000 0000) p9cr (01f8fh) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p9cr p9 port input/output control (specify bit wise) 0: input mode 1: output mode r/w p9ode (01f87h) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p9ode p9 port open-drain control (specify bit wise) 0: tri-state 1: open-drain r/w note 1: even when open-drain mode is selected, the protective diode remains connected. therefore, do not apply voltages ex- ceeding v dd . note 2: read-modify-write (rmw) operation executes at open-drain mode is selected, read out the output latch states. when any other instruction is executed, external pin states is read out. TMP88FW45AFG page 63 TMP88FW45AFG 5. input/output ports 5.10 port p9 (p97 to p90) page 64 6. time base timer (tbt) and divider output ( dvo) 6.1 time base timer the time base timer generates time base for key scanning, dynamic displaying, etc. it also provides a time base timer interrupt (inttbt). an inttbt ( time base timer interrupt ) is generated on the first falling edge of source clock ( the divider output of the timing generator which is selected by tbtck. ) after time base timer has been enabled. the divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period ( figure 6-2 ). the interrupt frequency (tbtck) must be selected with the time base timer disabled (tbten="0"). (the interrupt frequency must not be changed with the disable from the enable state.) both frequency selection and enabling can be performed simultaneously. figure 6-1 time base timer configuration figure 6-2 time base timer interrupt example :set the time base timer frequency to fc/2 16 [hz] and enable an inttbt interrupt. ld (tbtcr) , 00000010b ; tbtck 010 (freq. set) ld (tbtcr) , 00001010b ; tbten 1 (tbt enable) di set (eirl) . 6 ei TMP88FW45AFG page 65 source clock enable tbt interrupt period tbtcr time base timer is controled by time base timer control register (tbtcr). time base timer control register 7 6 5 4 3 2 1 0 tbtcr (00036h) (dvoen) (dvock) 0 tbten tbtck (initial value: 0000 0000) tbten time base timer enable / disable 0: disable 1: enable tbtck time base timer interrupt frequency select : [hz] normal, idle mode r/w dv1ck=0 dv1ck=1 000 fc/2 23 fc/2 24 001 fc/2 21 fc/2 22 010 fc/2 16 fc/2 17 011 fc/2 14 fc/2 15 100 fc/2 13 fc/2 14 101 fc/2 12 fc/2 13 110 fc/2 11 fc/2 12 111 fc/2 9 fc/2 10 note 1: fc; high-frequency clock [hz], *; don't care note 2: always set "0" in bit4 on tbtcr register. table 6-1 time base timer interrupt frequency ( example : fc = 20.0 mhz ) tbtck time base timer interrupt frequency [hz] normal, idle mode dv1ck = 0 dv1ck = 1 000 2.38 1.20 001 9.53 4.78 010 305.18 153.50 011 1220.70 610.35 100 2441.40 1220.70 101 4882.83 2441.40 110 9765.63 4882.83 111 39063.00 19531.25 TMP88FW45AFG 6. time base timer (tbt) 6.1 time base timer page 66 6.2 divider output ( dvo) approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. divider output is from dvo pin. figure 6-3 divider output the divider output is controlled by the time base timer control register (tbtcr). time base timer control register 7 6 5 4 3 2 1 0 tbtcr (00036h) dvoen dvock "0" (tbten) (tbtck) (initial value: 0000 0000) dvoen divider output enable / disable 0: disable 1: enable r/w dvock divider output ( dvo) frequency selection: [hz] normal, idle mode r/w dv1ck=0 dv1ck=1 00 fc/2 13 fc/2 14 01 fc/2 12 fc/2 13 10 fc/2 11 fc/2 12 11 fc/2 10 fc/2 11 note 1: selection of divider output frequency (dvock) must be made while divider output is disabled (dvoen="0"). also, in other words, when changing the state of the divider output frequency from enabled (dvoen="1") to disable(dvoen="0"), do not change the setting of the divider output frequency. note 2: in case of using dvo output, set output mode by p1cr register after setting the related port output latch to "1" by p1dr register. note 3: fc; high-frequency clock [hz], *; don't care note 4: be sure to write "0" to tbtcr register bit 4. example : 2.44 khz pulse output (fc = 20.0 mhz) port setting ld (tbtcr) , 00000000b ; dvock "00" ld (tbtcr) , 10000000b ; dvoen "1" TMP88FW45AFG page 67 tbtcr output latch port output latch mpx dvoen tbtcr table 6-2 divider output frequency ( example : fc = 20.0 mhz ) dvock divider output frequency [hz] normal, idle mode dv1ck=0 dv1ck=1 00 2.4415 k 1.22075 k 01 4.8825 k 2.4415 k 10 9.765 k 4.8825 k 11 19.5325 k 9.765 k TMP88FW45AFG 6. time base timer (tbt) 6.2 divider output ( dvo) page 68 7. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidly the cpu malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the cpu to a system recovery routine. the watchdog timer signal for detecting malfunctions can be programmed only once as reset request or pseudo non-maskable interrupt request. upon the reset release, this signal is initialized to reset request. when the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt. note:care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 7.1 watchdog timer configuration figure 7-1 watchdog timer configuration TMP88FW45AFG page 69 0034 h overflow wdt output internal reset binary counters wdtout writing clear code writing disable code wdten wdtt 2 0035 h watchdog timer control registers wdtcr1 wdtcr2 intwdt interrupt request interrupt request reset request reset release clock clear 1 2 controller q sr s r q selector fc/2 23 ,fc/2 24 fc/2 21 ,fc/2 22 fc/2 19 ,fc/2 20 fc/2 17 ,fc/2 18 7.2 watchdog timer control the watchdog timer is controlled by the watchdog timer control registers (wdtcr1 and wdtcr2). the watchdog timer is automatically enabled after the reset release. 7.2.1 malfunction detection methods using the watchdog timer the cpu malfunction is detected, as shown below. 1. set the detection time, select the output, and clear the binary counter. 2. clear the binary counter repeatedly within the specified detection time. if the cpu malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. when wdtcr1 watchdog timer control register 1 wdtcr1 (0034h) 7 6 5 4 3 2 1 0 wdten wdtt wdtout (initial value: **** 1001) wdten watchdog timer enable/disable 0: disable (writing the disable code to wdtcr2 is required.) 1: enable write only wdtt watchdog timer detection time [s] normal mode write only dv1ck = 0 dv1ck = 1 00 2 25 /fc 2 26 /fc 01 2 23 /fc 2 24 /fc 10 2 21 fc 2 22 fc 11 2 19 /fc 2 20 /fc wdtout watchdog timer output select 0: interrupt request 1: reset request write only note 1: after clearing wdtcr1 7.2.3 watchdog timer disable to disable the watchdog timer, set the register in accordance with the following procedures. setting the register in other procedures causes a malfunction of the microcontroller. 1. set the interrupt master flag (imf) to 0. 2. set wdtcr2 to the clear code (4eh). 3. set wdtcr1 7.2.5 watchdog timer reset when a binary-counter overflow occurs while wdtcr1 TMP88FW45AFG 7. watchdog timer (wdt) 7.2 watchdog timer control page 74 8. oscillation frequency detector 8.1 configuration the oscillation frequency detector generates a reset for i/o if the oscillation of high frequency is lower than a lower detection frequency, or higher than an upper detection frequency. each frequency is specified by clksmn and clksmx register. an initial value of lower detection frequency is 8.8mhz which is a harmonics of +10% of 16mhz, and that of upper detection frequency is 20mhz which is a maximum frequency in operating condition. for details, refer to figure 8-1. to change the detection frequency, clksmn and clksmx registers are used. clksmn and clksmx can be written when the oscillation frequency detection is disabled and writing to clksmn/clksmx is enabled by setting "f9h" to clkscr1. since the oscillation frequency detection is disabled after an external reset input, write "f9h" to clkscr1 and write "e4h" to clkscr2 register to enable its function. when the TMP88FW45AFG detects the out of frequency specified clksmn and clksmx register, all i/os become high impedance by reset. by the oscillation frequency detection reset, all i/os except power supply pins, reset, xin and xout become high impedance. if oscillation frequency detection reset is generated by detecting the stopping of high frequency, the internal circuities such as registers hold the condition at the timing of oscillation stop. to initialize these internal circuitries, an at external re-starting of oscillation is needed. note 1: though the harmonics of 16mhz is 32mhz, upper detection frequency is set to 20mhz to avoid an erratic operation caused by exceeding 20mhz. note 2: the oscillation frequency detection reset is available only in normal and idle modes. in stop modes, the oscillation frequency detection reset is disabled automatically. figure 8-1 detection frequency range figure 8-2 oscillation frequency detector TMP88FW45AFG page 75 fc r f r o osc. enable xin xout vdd vdd oscillation frequency detector oscillation frequency detection reset fc [mhz] 16 28.8 8 8.8 subharmonics of 16mhz harmonics of 16mhz-10% operating conditions area 20 16mhz r vdd [v] 14.4 17.6 4.5 5.5 if the calculated detection frequency is lower than 8mhz or higher than 20mhz, the detection frequency should be set within operating condition. 8.2 control the oscillation frequency detection is controlled by oscillation frequency detection control register 2 (clkscr2). the detection frequency is specified by lower/higher detection frequency setting register (clksmn, clksmx). writing to clkscr2/clksmn/clksmx is controlled by oscillation frequency control register 1 (clkscr1). oscillation frequency detection control register 1 clkscr1 (1f7fh) 7 6 5 4 3 2 1 0 initial value( 0000 0110) clkscr1 writing control of clkscr2, clksmn and clksmx registers 06h: disabling of writing to clkscr2/clksmn/clksmx f9h: enabling of writing to clkscr2/clksmn/clksmx others: reserved (note 1) r/w note 1: only "06h" and "f9h" is valid to clkscr1. if other value than "06h" and "f9h" is written to clkscr1, "06h" is written to clkscr1 automatically. note 2: clkscr1 is not initialized by an internal factor reset including oscillation frequency detection reset. to initialize this registers, set the reset pin (external factor reset) to the low level. oscillation frequency detection control register 2 clkscr2 (1f7ch) 7 6 5 4 3 2 1 0 initial value( 0000 0000) clkscr2 control the oscillation fre- quency detection circuit behavior 00h: disable e4h: enable others: reserved (note 1) r/w note 1: only "00h" and "e4h" is valid to clkscr2. writing other value than "00h" and "e4h" to clkscr2 with clkscr1="f9h" is ignored. note 2: writing to clkscr2 is protected by setting "06h" to clkscr1 but reading from clkscr2 is always enabled without setting of clkscr1. note 3: clkscr2 is not initialized by an internal factor reset including oscillation frequency detection reset. to initialize this registers, set the reset pin (external factor reset) to the low level. lower detection frequency setting register clksmn (1f7dh) 7 6 5 4 3 2 1 0 read/write initial value( 0010 0000) higher detection frequency setting register clksmx (1f7eh) 7 6 5 4 3 2 1 0 read/write initial value(0100 0000) note 1: clksmn and clksmx can not be written when the oscillation frequency detection circuit is enabled (clkscr2="e4h") or writing is disabled with clkscr1="06h". an attempt to write clksmn and clksmx can not complete a write oper- ation. note 2: writing to clksmn/clksmx is protected by setting "06h" to clkscr1 but reading from clksmn/clksmx is always enabled without setting of clkscr1. note 3: specify an appropriate value to clksmn and clksmx depending on the clock frequency to be used under the condition of clksmn 8.3 function 8.3.1 enabling and disabling the oscillation frequency detection writing "e4h" to clkscr2 with clkscr1="f9h" enables the oscillation frequency detection, and writing "00h" to clkscr2 with clkscr1="f9h" disables the oscillation frequency detection. setting "f9h" to clkscr1 enables writing to clkscr2 and setting "06h" to clkscr1 disables writing to clkscr2. reading from clkscr2 is always enabled without setting of clkscr1. clkscr1 is initialized to "06h" by external reset and clkscr2 is initialized to "00h" by external reset. however, clkscr1 and clkscr2 are not initialized by internal reset which are system clock, address trap, watchdog timer reset and oscillation frequency detection reset. note:after writing data to clkscr2, set "06h" to clkscr1 to protect clkscr2 register. when stop mode is executed with clkscr2=e4h, the oscillation frequency detection is automatically disabled. after releasing stop and warming up period, the oscillation frequency detection is enabled. in serial prom mode for flash, the oscillation frequency detection is disabled. the oscillation frequency detection is available only in normal and idle mode. table 8-1 shows the availability of oscillation frequency detector. table 8-1 availability of oscillation frequency detector operating mode oscillation frequency detection all i/os condition after oscillation frequency detection reset normal available high impedance idle available high impedance stop (including warming up period) oscillation frequency detection is disabled automatically. reset by oscillation frequency detection reset available high impedance reset by internal reset (note 1) available high impedance reset by external reset disable - serial prom disable - note 1: internal reset ; watchdog timer reset, address trap reset, system clock reset and oscillation frequency detection reset. figure 8-3 availabirity of oscillation frequency detection TMP88FW45AFG page 77 high-frequency clock vdd external reset input internal reset oscillation frequency detector control external reset internal reset external reset normal or idle mode normal or idle mode normal or idle mode normal or idle mode stop mode including warming up disable disable disable enable enable enable enabling by writting e4h to clkscr enabling by writting e4h to clkscr 8.3.2 setting the lower and higher frequency for detection the detection frequency is controlled by clksmn and clksmx registers. these registers can not be written while the oscillation frequency detection circuit is enabled or writing is disabled by setting "06h" to clkscr1. therefore, to change the detection frequency, disable the oscillation frequency detection by setting "00h" to clkscr2 with clkscr1="f9h". the detection frequency is calculated by the formula shown below. note 1: after writing data to clksmn and clksmx, set "06h" to clkscr1 to protect clksmn and clksmx. note 2: specify an appropriate value to clksmn and clksmx depending on the clock frequency to be used under the condition of clksmn figure 8-4 oscillation frequency detection reset timing TMP88FW45AFG page 79 high-frequency clock when the high-frequency clock becomes abnormal stable abnormal stable oscillation frequency detection reset t ofd high-frequency clock when the high-frequency clock stops stable stop stable oscillation frequency detection reset t ofd all i/os hi-z all i/os hi-z clocked reset cpu address fffe ffff when normal oscillation continues for some period, the oscillation frequency detection reset is released. t ofd t ofd when normal oscillation continues for some period, the oscillation frequency detection reset is released. clocked reset is generated after resuming of frequency. when normal oscillation continues for some period, the oscillation frequency detection reset is released. TMP88FW45AFG 8. oscillation frequency detector 8.3 function page 80 9. 16-bit timercounter 1 (tc1) 9.1 configuration figure 9-1 timercounter 1 (tc1) TMP88FW45AFG page 81 :::? pin tc1 :w:?::? mett1 start capture clear source clock ppg output mode write to tc1cr 16-bit up-counter clear tc1drb selector tc1dra tc1cr tc1 control register match inttc1 interript tff1 acap1 tc1ck window mode set toggle q 2 toggle set clear q y a d b c s b a y s tc1s clear mppg1 ppg output mode internal reset s enable mcap1 s y a b tc1s 2 set clear command start decoder external trigger start edge detector note: function i/o may not operate depending on i/o port setting. for more details, see the chapter "i/o port". port (note) q pulse width measurement mode falling rising trigger external cmp 16-bit timer register a, b pulse width measurement mode port (note) fc/2 11 , fc/2 12 fc/2 7 , fc/2 8 fc/2 3 , fc/2 4 9.2 timercounter control the timercounter 1 is controlled by the timercounter 1 control register (tc1cr) and two 16-bit timer registers (tc1dra and tc1drb). timer register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc1dra (0011h, 0010h) tc1drah (0011h) tc1dral (0010h) (initial value: 1111 1111 1111 1111) read/write tc1drb (0013h, 0012h) tc1drbh (0013h) tc1drbl (0012h) (initial value: 1111 1111 1111 1111) read/write (write enabled only in the ppg output mode) timercounter 1 control register tc1cr (000fh) 7 6 5 4 3 2 1 0 tff1 acap1 mcap1 mett1 mppg1 tc1s tc1ck tc1m read/write (initial value: 0000 0000) tff1 timer f/f1 control 0: clear 1: set r/w acap1 auto capture control 0 : auto-capture disable 1 : auto-capture enable r/w mcap1 pulse width measurement mode control 0 :double edge capture 1 : single edge capture r/w mett1 external trigger timer mode control 0 : trigger start 1 : trigger start and stop mppg1 ppg output control 0 : continuous pulse generation 1 : one-shot tc1s tc1 start control timer extrig- ger event win- dow pulse ppg r/w 00: stop and counter clear o o o o o o 01: command start o - - - - o 10: rising edge start (ex-trigger/pulse/ppg) rising edge count (event) positive logic count (window) - o o o o o 11: falling edge start (ex-trigger/pulse/ppg) falling edge count (event) negative logic count (window) - o o o o o tc1ck tc1 source clock select [hz] normal, idle mode r/w dv1ck = 0 dv1ck = 1 00 fc/2 11 fc/2 12 01 fc/2 7 fc/2 8 10 fc/2 3 fc/2 4 11 external clock (tc1 pin input) tc1m tc1 operating mode se- lect 00: timer/external trigger timer/event counter mode 01: window mode 10: pulse width measurement mode 11: ppg (programmable pulse generate) output mode r/w note 1: fc: high-frequency clock [hz] note 2: the timer register consists of two shift registers. a value set in the timer register becomes valid at the rising edge of the first source clock pulse that occurs after the upper byte (tc1drah and tc1drbh) is written. therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). writing only the lower byte (tc1dral and tc1drbl) does not enable the setting of the timer register. TMP88FW45AFG 9. 16-bit timercounter 1 (tc1) 9.2 timercounter control page 82 note 3: to set the mode, source clock, ppg output control and timer f/f control, write to tc1cr during tc1cr 9.3 function timercounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 9.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register 1a (tc1dra) value is detected, an inttc1 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. setting tc1cr figure 9-2 timer mode timing chart TMP88FW45AFG page 85 match detect acap1 tc1drb tc1dra inttc1 interruput request source clock counter source clock counter ? (a) timer mode (b) auto-capture ? 7 6 345 0 timer start 12 3 2 1 4 0 counter clear capture n + 1 n n n m + 2 m + 1 m m capture m + 2 m + 1 n + 1 n m ? 1 m ? 1 m ? 2 n ? 1 n ? 1 n ? 1 9.3.2 external trigger timer mode in the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. for the trigger edge used to start counting, either the rising or falling edge is defined in tc1cr figure 9-3 external trigger timer mode timing chart TMP88FW45AFG page 87 inttc1 interrupt request source clock up-counter tc1dra tc1 pin input inttc1 interrupt request source clock up-counter tc1dra tc1 pin input 0 at the rising edge (tc1s = 10) at the rising edge (tc1s = 10) (a) trigger start (mett1 = 0) count start match detect count start 0 1 2 3 4 2 3 n (b) trigger start and stop (mett1 = 1) count start count start 0 1 2 3 m 0 n n 0 count clear note: m < n count clear 1 2 3 1 n m ? 1 n ? 1 match detect count clear 9.3.3 event counter mode in the event counter mode, the up-counter counts up at the edge of the input pulse to the tc1 pin. either the rising or falling edge of the input pulse is selected as the count up edge in tc1cr 9.3.4 window mode in the window mode, the up-counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the tc1 pin (window pulse) and the internal source clock. either the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. when a match between the up-counter and the tc1dra value is detected, an inttc1 interrupt is generated and the up-counter is cleared. define the window pulse to the frequency which is sufficiently lower than the internal source clock programmed with tc1cr 9.3.5 pulse width measurement mode in the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. either the rising or falling edge of the internal clock is selected as the trigger edge in tc1cr example :duty measurement (resolution fc/2 7 [hz], cgcr figure 9-6 pulse width measurement mode TMP88FW45AFG 9. 16-bit timercounter 1 (tc1) 9.3 function page 92 tc1drb inttc1 interrupt request interrupt request tc1 pin input counter internal clock (mcap1 = "1") 23 n count start count start trigger (tc1s = "10") 1 3 2 1 4 0 n 0 capture n - 1 tc1drb inttc1 tc1 pin input counter internal clock (mcap1 = "0") 12 n count start count start (tc1s = "10") 3 2 1 4 0 n capture capture n + 1 m - 2 n + 3 n + 2 n + 1 m - 1 m0 m [application] high-or low-level pulse width measurement [application] (1) cycle/frequency measurement (2) duty measurement (a) single-edge capture (b) double-edge capture 9.3.6 programmable pulse generate (ppg) output mode in the programmable pulse generation (ppg) mode, an arbitrary duty pulse is generated by counting performed in the internal clock. to start the timer, tc1cr figure 9-7 ppg output figure 9-8 ppg mode timing chart TMP88FW45AFG 9. 16-bit timercounter 1 (tc1) 9.3 function page 94 inttc1 tc1dra internal clock counter tc1drb tc1dra ppg pin output 0 inttc1 interrupt request interrupt request 12 m01 2 n m01 n 2 n n + 1 n + 1 m (a) continuous pulse generation (tc1s = 01) tc1drb trigger count start timer start counter internal clock tc1 pin input ppg pin output 0 1m n n n + 1 m 0 (b) one-shot pulse generation (tc1s = 10) match detect note: m > n note: m > n [application] one-shot pulse output q r d ppg pin function output port output enable i/o port output latch shared with ppg output data output toggle set clear q tc1cr 10. 16-bit timer (ctc) 10.1 configuration figure 10-1 ctc block diagram TMP88FW45AFG page 95 ctc1cr2 ctc1cr1 3 2 2 2 3 3 toggle q set clear ? ctc1s ctc1sm ctc1se ctc1cy ctc1e ? rising edge falling edge s a y b ctc pin h a b c d y e s fc/2 11 or fc/2 12 fc/2 7 or fc/2 8 fc/2 5 or fc/2 6 fc/2 3 or fc/2 4 fc/2 2 or fc/2 3 fc/2 or fc/2 2 ctc1ck ctc1s ctc1res extrgdis ctc1reg ctc1ck ctc1ff0 ppgff0 ctc1m ctc1cy ctc1se ctc1e ctc1sm ctc1m ctc1ff0 ppgff0 ctc1m ctc1reg last coincidence interrupt stop trigger clear start start control read/write control and clear interrupt select write register select read register ctc1dra ctc1drb ctc1drc 16-bit up counter intctc1 interrupt ppg2 pin edge detection comparator extrgdis 10.2 control compare timer/counter 1 is controlled using compare timer/counter 1 control registers (ctc1cr1 and ctc1cr2), as well as three 16-bit timer registers (ctc1dra, ctc1drb, and ctc1drc). compare timer registers (ctc1drh: 00017h, ctc1drl: 00016h) ctc1dra 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write only (initial value: ******** ********) ctc1drah ctc1dral ctc1drb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write only (initial value: ******** ********) ctc1drbh ctc1drbl ctc1drc 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 write only (initial value: ******** ********) ctc1drch ctc1drcl note:ctc1dra, ctc1drb, and ctc1drc are write-only registers and must not be used with any of the read-modify- write instructions such as set, clr, etc. compare timer/counter 1 control registers (ctc1cr2: 00015h, ctc1cr1: 00014h) ctc1cr1 lower address 7 6 5 4 3 2 1 0 r/w (initial value: 00000000) ctc1res ppgff0 ctc1m ctc1cy ctc1se ctc1e ctc1sm ctc1s ctc1cr2 upper address 7 6 5 4 3 2 1 0 r/w (initial value: *0000000) * ex- trgdis ctc1reg ctc1ck ctc1ff0 note 1: *: dont care note 2: the ctc1cr1 setting-up the ctc1cr1 register ctc1s control start 0: stop and clear counter 1: command start timer event ppg r/w ctc1sm select start 0: software start 1: external trigger start ctc1e select external trigger edge 0: enable one edge 1: enable both edges ctc1se select external trigger start edge 0: rising edge 1: falling edge ctc1cy select cycle 0: successive 1: one shot ctc1m set operation mode 0: timer/event counter modes 1: ppg (programmable pulse generator) output mode ppgff0 select ppg output 0: forward output immediately after start 1: reverse output immediately after start ctc1res reset all 0: normal operation 1: ctc1 reset setting-up the ctc1cr2 register ctc1ff0 control timer output f/f0 0: clear 1: set r/w ctc1ck select timer/counter clock source unit: hz normal and idle modes dv1ck = 0 dv1ck = 1 timer event ppg 000 fc/2 11 fc/2 12 ? 001 fc/2 7 fc/2 8 ? 010 fc/2 5 fc/2 6 ? 011 fc/2 3 fc/2 4 ? 100 fc/2 2 fc/2 3 ? note3 101 fc/2 fc/2 2 ? 110 ? ? 111 external clock input (ctc1 pin input) - ctc1reg set registers used by timer/ counter 00: ctc1dra 01: ctc1dra + ctc1drb 10: ctc1dra + ctc1drb + ctc1drc 11: reserved 1reg 2reg 3reg extrgdis external trigger input note4 0: enable external trigger input 1: disable external trigger input note 1: fc: clock [hz] note 2: make sure the timer/counter is idle (ctc1cr1 note 10: specifying ctc1cr1 10.3 function compare timer/counter 1 has three modes: timer, event counter, and programmable pulse generator output modes. 10.3.1 timer mode with software start in this mode, the timer/counter (16-bit counter) counts up synchronously with the internal clock. when the counter value and the set value of compare timer register 1a (ctc1dra) match, an intctc1 interrupt is generated and the counter is cleared. after the counter is cleared, it restarts and continues counting up. table 10-1 internal clock source for compare timer/counter 1 (example: fc = 20 mhz) ctc1ck normal and idle modes dv1ck = 0 dv1ck = 1 resolution [s] maximum setting time [s] resolution [s] maximum setting time [s] 000 102.4 6.71 204.8 13.42 001 6.4 0.419 12.8 0.839 010 1.6 0.105 3.2 0.210 011 0.4 26.21 m 0.8 52.43 m 100 0.2 13.11 m 0.4 26.21 m 101 0.1 6.55 m 0.2 13.11 m 110 - - - - figure 10-2 timer mode timing chart note:if the ctc input port (p47) is set for input mode, the timer/counter is reset by an input edge on port. when using the timer/counter as an ordinary timer, set ctc1cr2 10.3.2 timer mode with external trigger start in this timer mode, the timer/counter starts counting as triggered by input on ctc pin (rising or falling edge selected with ctc1cr1 figure 10-4 external trigger mode timing chart 10.3.3 event counter mode in this mode, the timer/counter counts up at the active edge on ctc pin input (rising or falling edge selected with the ctc1cr1 table 10-2 external clock source for compare timer/counter 1 normal and idle modes maximum applied frequency [hz] up to fc/2 2 minimum pulse width 2 2 /fc and over 10.3.4 programmable pulse generate (ppg) output mode the timer/counter starts counting as a command or edge on ctc pin input (rising/falling edge and one/both edges respectively selected with the ctc1cr1 figure 10-6 one register command start mode timing chart figure 10-7 two register one edge trigger start mode timing chart TMP88FW45AFG page 103 (ii) two registers used (ctc1reg = 01) when set to the external trigger rising edge start and the one edge enable. ctc pin input counter internal clock timer register a timer register b 1 m m+1 m m+1 1 n 0 intctc1 interrupt start stop m n ppg2 pin output 1 2 0 n successive initial value ctc pin input counter internal clock timer register a timer register b 1 m m+1 0 n 0 intctc1 interrupt start start m n ppg2 pin output 1 one shot a) successive b) one shot (i) one register used (ctc1reg = 00) when set to command start. ctc pin input counter timer register a 11 1 n n 0 intctc1 interrupt command start n ppg2 pin output 1 n 1 2 3 n successive figure 10-8 two register both edges trigger start mode timing chart TMP88FW45AFG 10. 16-bit timer (ctc) 10.3 function page 104 when set to the external trigger rising edge start and the both edges enable. ctc pin input counter internal clock timer register a timer register b 1 m m+1 m 1 n 0 intctc1 interrupt start start stop m n ppg2 pin output 1 0 successive initial value ctc pin input counter internal clock timer register a timer register b 1 m m+1 mn m+1 0 11 n 2 00 0 intctc1 interrupt start m n ppg2 pin output m 1 m+1 0 one shot start start start a) successive b) one shot note:in the single-shot mode, the ppg pin output is not toggled at the last register match; it stays at the value specified with ctc1cr2 detail operation at start that varies depending on how ctc1cr2 11. 8-bit timercounter 3 (tc3) 11.1 configuration note:function input may not operate depending on i/o port setting. for more details, see the chapter "i/o port". figure 11-1 timercounter 3 (tc3) TMP88FW45AFG page 107 tc3ck tc3s fc/2 13 , fc/2 14 fc/2 12 , fc/2 13 fc/2 11 , fc/2 12 fc/2 10 , fc/2 11 fc/2 9 , fc/2 , fc/2 9 , fc/2 8 3 source clock capture clear tc3s inttc3 interrupt tc3 contorol register 8-bit timer register overflow detect h a b c d e f g s tc3m tc3cr edge detector tc3drb tc3dra capture acap tc3s falling rising a y b s match detect y 8-bit up-counter tc3 pin port (note) cmp fc/2 8 fc/2 7 10 11.2 timercounter control the timercounter 3 is controlled by the timercounter 3 control register (tc3cr) and two 8-bit timer registers (tc3dra and tc3drb). timer register and control register tc3dra (001ch) 7 6 5 4 3 2 1 0 read/write (initial value: 1111 1111) tc3drb (001dh) read only (initial value: 1111 1111) tc3cr (001eh) 7 6 5 4 3 2 1 0 acap tc3s tc3ck tc3m (initial value: *0*0 0000) acap auto capture control 0: - 1: auto capture r/w tc3s tc3 start control 0: stop and counter clear 1: start r/w tc3ck tc3 source clock select [hz] normal, idle mode r/w dv1ck=0 dv1ck=1 000 fc/2 13 fc/2 14 001 fc/2 12 fc/2 13 010 fc/2 11 fc/2 12 011 fc/2 10 fc/2 11 100 fc/2 9 fc/2 10 101 fc/2 8 fc/2 9 110 fc/2 7 fc/2 8 111 external clock (tc3pin input) tc3m tc3 operating mode se- lect 0: timer/event counter mode 1: capture mode r/w note 1: fc: high-frequency clock [hz], *: dont care note 2: set the operating mode and source clock when timercounter stops (tc3cr 11.3 function timercounter 3 has three types of operating modes: timer, event counter and capture modes. 11.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register 3a (tc3dra) value is detected, an inttc3 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. setting tc3cr figure 11-3 timer mode timing chart TMP88FW45AFG 11. 8-bit timercounter 3 (tc3) 11.3 function page 110 match detect tc3cr 11.3.2 event counter mode in the event counter mode, the up-counter counts up at the rising edge of the input pulse to the tc3 pin. when a match between the up-counter and tc3dra value is detected, an inttc3 interrupt is generated and up-counter is cleared. after being cleared, the up-counter restarts counting at each rising edge of the input pulse to the tc3 pin. since a match is detected at the falling edge of the input pulse to tc3 pin, an inttc3 interrupt request is generated at the falling edge immediately after the up-counter reaches the value set in tc3dra. the maximum applied frequencies are shown in table 11-2. the pulse width larger than one machine cycle is required for high-going and low-going pulses. setting tc3cr 11.3.3 capture mode in the capture mode, the pulse width, frequency and duty cycle of the pulse input to the tc3 pin are measured with the internal clock. the capture mode is used to decode remote control signals, and identify ac50/60 hz. when the falling edge of the tc3 input is detected after the timer starts, the up-counter value is captured into tc3drb. hereafter, whenever the rising edge is detected, the up-counter value is captured into tc3dra and the inttc3 interrupt request is generated. the up-counter is cleared at this time. generally, read tc3drb and tc3dra during inttc3 interrupt processing. after the up-counter is cleared, counting is continued and the next up-counter value is captured into tc3drb. when the rising edge is detected immediately after the timer starts, the up-counter value is captured into tc3dra only, but not into tc3drb. the inttc3 interrupt request is generated. when the read instruction is executed to tc3drb at this time, the value at the completion of the last capture (ff immediately after a reset) is read. the minimum input pulse width must be larger than one cycle width of the source clock programmed in tc3cr 12. 8-bit timercounter 4 (tc4) 12.1 configuration figure 12-1 timercounter 4 (tc4) TMP88FW45AFG page 113 pwm output mode clear 3 2 source clock 8-bit up-counter overflow detect toggle clear timer f/f match detect s y 0 1 y s s 1 0 y pdo mode port (note) ::?:?:? (note) a b c d e f g h y s cmp note: function i/o may not operate depending on i/o port setting. for more details, see the chapter "i/o port". tc4cr tc4dr inttc4 interrupt tc4s tc4s tc4s tc4m tc4ck tc4 pin pwm4 / pdo4 / pin fc/2 11 , fc2 12 fc/2 7 , fc2 8 fc/2 5 , fc2 6 fc/2 3 , fc2 4 fc/2 2 , fc2 3 fc/2, fc2 2 fc, fc/2 12.2 timercounter control the timercounter 4 is controlled by the timercounter 4 control register (tc4cr) and timer registers 4 (tc4dr). timer register and control register tc4dr (001bh) 7 6 5 4 3 2 1 0 read/write (initial value: 1111 1111) tc4cr (001ah) 7 6 5 4 3 2 1 0 tc4s tc4ck tc4m read/write (initial value: **00 0000) tc4s tc4 start control 0: stop and counter clear 1: start r/w tc4ck tc4 source clock select [hz] normal, idle mode r/w dv1ck = 0 dv1ck = 1 000 fc/2 11 fc/2 12 001 fc/2 7 fc/2 8 010 fc/2 5 fc/2 6 011 fc/2 3 fc/2 4 100 fc/2 2 fc/2 3 101 fc/2 2 110 (fc) note8 (fc/2) note8 111 external clock (tc4 pin input) tc4m tc4 operating mode se- lect 00: timer/event counter mode 01: reserved 10: programmable divider output (pdo) mode 11: pulse width modulation (pwm) output mode r/w note 1: fc: high-frequency clock [hz], *: dont care note 2: to set the timer registers, the following relationship must be satisfied. 1 tc4dr 255 note 3: to start timer operation (tc4cr 12.3 function timercounter 4 has four types of operating modes: timer, event counter, programmable divider output (pdo), and pulse width modulation (pwm) output modes. 12.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the tc4dr value is detected, an inttc4 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. table 12-1 internal source clock for timercounter 4 (example: fc = 20 mhz) tc4ck normal, idle mode dv1ck = 0 dv1ck = 1 resolution [s] maximum time setting [ms] resolution [s] maximum time setting [ms] 000 102.4 26.11 204.8 52.22 001 6.4 1.63 12.8 3.28 010 1.6 0.41 3.2 0.82 011 0.4 0.10 0.8 0.20 12.3.2 event counter mode in the event counter mode, the up-counter counts up at the rising edge of the input pulse to the tc4 pin. when a match between the up-counter and the tc4dr value is detected, an inttc4 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting at rising edge of the tc4 pin. since a match is detected at the falling edge of the input pulse to the tc4 pin, the inttc4 interrupt request is generated at the falling edge immediately after the up-counter reaches the value set in tc4dr. the minimum pulse width applied to the tc4 pin are shown in table 12-2. the pulse width larger than two machine cycles is required for high- and low-going pulses. note:the event counter mode can used in the normal and idle modes only. table 12-2 external source clock for timercounter 4 minimum pulse width normal, idle mode high-going 2 3 /fc low-going 2 3 /fc 12.3.3 programmable divider output (pdo) mode the programmable divider output (pdo) mode is used to generated a pulse with a 50% duty cycle by counting with the internal clock. when a match between the up-counter and the tc4dr value is detected, the logic level output from the pdo4 pin is switched to the opposite state and inttc4 interrupt request is generated. the up-counter is cleared at this time and then counting is continued. when a match between the up-counter and the tc4dr value is detected, the logic level output from the pdo4 pin is switched to the opposite state again and inttc4 interrupt request is generated. the up-counter is cleared at this time, and then counting and pdo are continued. TMP88FW45AFG page 115 when the timer is stopped, the pdo4 pin is high. therefore, if the timer is stopped when the pdo4 pin is low, the duty pulse may be shorter than the programmed value. example :generating 1024 hz pulse (fc = 20.0 mhz and cgcr figure 12-3 pwm output mode timing chart (tc4) table 12-3 pwm mode (example: fc = 20 mhz) tc4ck normal, idle mode dv1ck = 0 dv1ck = 1 resolution [ns] cycle [s] resolution [ns] cycle [s] 000 - - - - 001 - - - - 010 - - - - 011 400 102.4 800 204.8 100 200 51.2 400 102.4 101 100 25.6 200 51.2 110 - - - - TMP88FW45AFG page 117 internal clock shift register counter n 0 ? ? 1 n + 1 ff 0 1 n n + 1 ff 01 m pwm cycle match detect mp n n m data shift rewrite data shift match detect match detect data shift n n m rewrite rewrite pwm4 pin inttc4 interrupt request timer f/f tc4dr tc4cr TMP88FW45AFG 12. 8-bit timercounter 4 (tc4) 12.3 function page 118 13. 8-bit timercounter 5,6(tc5, 6) 13.1 configuration figure 13-1 8-bit timercounter 5, 6 TMP88FW45AFG page 119 8-bit up-counter decode en a y b s a b y c d e f g h s a y b s s a y b toggle q set clear 8-bit up-counter a b y c d e f g h s decode en toggle q set clear pwm mode pdo, ppg mode pdo mode pwm, ppg mode pwm mode pwm mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode timer, event counter mode overflow overflow timer, event couter mode 16-bit mode clear clear fc/2 7 , fc/2 8 fc/2 5 , fc/2 6 fc/2 3 , fc/2 4 pdo, pwm, ppg mode pdo, pwm mode 16-bit mode fc/2 7 , fc/2 8 fc/2 5 , fc/2 6 fc/2 3 , fc/2 4 fc/2 11 , fc/2 12 fc/2 11 , fc/2 12 tc6cr tc5cr ttreg6 pwreg6 ttreg5 pwreg5 tc5 pin tc6 pin tc6s tc5s inttc5 interrupt request inttc6 interrupt request tff6 tff5 pdo 6 /pwm 6 / ppg 6 pin pdo 5 /pwm 5 / pin tc5ck tc6ck tc5m tc5s tff5 tc6m tc6s tff6 timer f/f6 timer f/f5 13.2 timercounter control the timercounter 5 is controlled by the timercounter 5 control register (tc5cr) and two 8-bit timer registers (ttreg5, pwreg5). timercounter 5 timer register ttreg5 (0022h) r/w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) pwreg5 (0024h) r/w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) note 1: do not change the timer register (ttreg5) setting while the timer is running. note 2: do not change the timer register (pwreg5) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. timercounter 5 control register tc5cr (0020h) 7 6 5 4 3 2 1 0 tff5 tc5ck tc5s tc5m (initial value: 0000 0000) tff5 time f/f5 control 0: 1: clear set r/w tc5ck operating clock selection [hz] normal, idle mode r/w dv1ck = 0 dv1ck = 1 000 fc/2 11 fc/2 12 001 fc/2 7 fc/2 8 010 fc/2 5 fc/2 6 011 fc/2 3 fc/2 4 100 - - 101 - - 110 - - 111 tc5 pin input tc5s tc5 start control 0: 1: operation stop and counter clear operation start r/w tc5m tc5m operating mode select 000: 001: 010: 011: 1**: 8-bit timer/event counter mode 8-bit programmable divider output (pdo) mode 8-bit pulse width modulation (pwm) output mode 16-bit mode (each mode is selectable with tc6m.) reserved r/w note 1: fc: high-frequency clock [hz] note 2: do not change the tc5m, tc5ck and tff5 settings while the timer is running. note 3: to stop the timer operation (tc5s= 1 0), do not change the tc5m, tc5ck and tff5 settings. to start the timer operation (tc5s= 0 1), tc5m, tc5ck and tff5 can be programmed. note 4: to use the timercounter in the 16-bit mode, set the operating mode by programming tc6cr the timercounter 6 is controlled by the timercounter 6 control register (tc6cr) and two 8-bit timer registers (ttreg6 and pwreg6). timercounter 6 timer register ttreg6 (0023h) r/w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) pwreg6 (0025h) r/ w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) note 1: do not change the timer register (ttreg6) setting while the timer is running. note 2: do not change the timer register (pwreg6) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. timercounter 6 control register tc6cr (0021h) 7 6 5 4 3 2 1 0 tff6 tc6ck tc6s tc6m (initial value: 0000 0000) tff6 timer f/f6 control 0: 1: clear set r/w tc6ck operating clock selection [hz] normal, idle mode r/w dv1ck = 0 dv1ck = 1 000 fc/2 11 fc/2 12 001 fc/2 7 fc/2 8 010 fc/2 5 fc/2 5 011 fc/2 3 fc/2 3 100 - - 101 - - 110 - - 111 tc6 pin input tc6s tc6 start control 0: 1: operation stop and counter clear operation start r/w tc6m tc6m operating mode select 000: 001: 010: 011: 100: 101: 110: 111: 8-bit timer/event counter mode 8-bit programmable divider output (pdo) mode 8-bit pulse width modulation (pwm) output mode reserved 16-bit timer/event counter mode warm-up counter mode 16-bit pulse width modulation (pwm) output mode 16-bit ppg mode r/w note 1: fc: high-frequency clock [hz] note 2: do not change the tc6m, tc6ck and tff6 settings while the timer is running. note 3: to stop the timer operation (tc6s= 1 0), do not change the tc6m, tc6ck and tff6 settings. to start the timer operation (tc6s= 0 1), tc6m, tc6ck and tff6 can be programmed. note 4: when tc6m= 1** (upper byte in the 16-bit mode), the source clock becomes the tc6 overflow signal regardless of the tc5ck setting. note 5: to use the timercounter in the 16-bit mode, select the operating mode by programming tc6m, where tc5cr note 7: the operating clock settings are limited depending on the timer operating mode. for the detailed descriptions, see table 13-1. note 8: the timer register settings are limited depending on the timer operating mode. for the detailed descriptions, see table 13-2. table 13-1 operating mode and selectable source clock (normal and idle modes) operating mode fc/2 11 fc/2 7 fc/2 5 fc/2 3 tc5 pin input tc6 pin input 8-bit timer - - 8-bit event counter - - - - 8-bit pdo - - 8-bit pwm - - 16-bit timer - - 16-bit event counter - - - - - 16-bit pwm - 16-bit ppg - note 1: for 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit pwm and 16-bit ppg), set its source clock on lower bit (tc5ck). note 2: : available source clock table 13-2 constraints on register values being compared operating mode register value 8-bit timer/event counter 1 (ttregn) 255 8-bit pdo 1 (ttregn) 255 8-bit pwm 2 (pwregn) 254 16-bit timer/event counter 1 (ttreg6, 5) 65535 16-bit pwm 2 (pwreg6, 5) 65534 16-bit ppg 1 (pwreg6, 5) < (ttreg6, 5) 65535 and (pwreg6, 5) + 1 < (ttreg6, 5) note:n = 5 to 6 TMP88FW45AFG 13. 8-bit timercounter 5,6(tc5, 6) 13.2 timercounter control page 122 13.3 function the timercounter 5 and 6 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (pdo), 8- bit pulse width modulation (pwm) output modes. the timercounter 5 and 6 (tc5, 6) are cascadable to form a 16- bit timer. the 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, 16-bit pulse width modulation (pwm) output and 16-bit programmable pulse generation (ppg) modes. 13.3.1 8-bit timer mode (tc5 and 6) in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register j (ttregj) value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. note 1: in the timer mode, fix tcjcr figure 13-2 8-bit timer mode timing chart (tc6) 13.3.2 8-bit event counter mode (tc5, 6) in the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the tcj pin. when a match between the up-counter and the ttregj value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting at the falling edge of the input pulse to the tcj pin. two machine cycles are required for the low- or high-level pulse input to the tcj pin. therefore, a maximum frequency to be supplied is fc/2 4 hz in the normal or idle mode. note 1: in the event counter mode, fix tcjcr example :generating 1024 hz pulse using tc6 (fc = 20.0 mhz) setting port ld (ttreg6), 3dh : 1/1024 2 7 /fc 2 = 3dh ld (tc6cr), 00010001b : sets the operating clock to fc/2 7 , and 8-bit pdo mode. ld (tc6cr), 00011001b : starts tc6. note 1: in the programmable divider output mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configuration in the programmable divider output mode, the new value programmed in ttregj is in effect immediately after programming. therefore, if ttregi is changed while the timer is running, an expected operation may not be obtained. note 2: when the timer is stopped during pdo output, the pdoj pin holds the output status when the timer is stopped. to change the output status, program tcjcr figure 13-4 8-bit pdo mode timing chart (tc6) TMP88FW45AFG 13. 8-bit timercounter 5,6(tc5, 6) 13.3 function page 126 12 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n ? internal source clock counter match detect match detect match detect match detect held at the level when the timer is stopped set f/f write of "1" tc6cr 13.3.4 8-bit pulse width modulation (pwm) output mode (tc5, 6) this mode is used to generate a pulse-width modulated (pwm) signals with up to 8 bits of resolution. the up- counter counts up using the internal clock. when a match between the up-counter and the pwregj value is detected, the logic level output from the timer f/fj is switched to the opposite state. the counter continues counting. the logic level output from the timer f/ fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. the inttcj interrupt request is generated at this time. since the initial value can be set to the timer f/fj by tcjcr figure 13-5 8-bit pwm mode timing chart (tc6) TMP88FW45AFG 13. 8-bit timercounter 5,6(tc5, 6) 13.3 function page 128 1 0 n n+1 ff 0 n n+1 ff 0 1 m m+1 ff 0 1 1 p n ? internal source clock counter m p mp n ? shift registar shift shift shift shift match detect match detect one cycle period match detect match detect n m p n tc6cr 13.3.5 16-bit timer mode (tc5 and 6) in the timer mode, the up-counter counts up using the internal clock. the timercounter 5 and 6 are cascadable to form a 16-bit timer. when a match between the up-counter and the timer register (ttreg5, ttreg6) value is detected after the timer is started by setting tc6cr figure 13-6 16-bit timer mode timing chart (tc5 and tc6) 13.3.6 16-bit event counter mode (tc5 and 6) in the event counter mode, the up-counter counts up at the falling edge to the tc5 pin. the timercounter 5 and 6 are cascadable to form a 16-bit event counter. when a match between the up-counter and the timer register (ttreg5, ttreg6) value is detected after the timer is started by setting tc6cr shifted by the inttcj interrupt request and loaded into pwreg6 and 5. while the timer is stopped, the values are shifted immediately after the programming of pwreg6 and 5. set the lower byte (pwreg5) and upper byte (pwreg5) in this order to program pwreg6 and 5. (programming only the lower or upper byte of the register should not be attempted.) if executing the read instruction to pwreg6 and 5 during pwm output, the values set in the shift register is read, but not the values set in pwreg6 and 5. therefore, after writing to the pwreg6 and 5, reading data of pwreg6 and 5 is previous value until inttc6 is generated. for the pin used for pwm output, the output latch of the i/o port must be set to 1. note 1: in the pwm mode, program the timer register pwreg6 and 5 immediately after the inttc6 interrupt request is generated (normally in the inttc6 interrupt service routine.) if the programming of pwregj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next inttc6 interrupt request is generated. note 2: when the timer is stopped during pwm output, the pwm 6 pin holds the output status when the timer is stopped. to change the output status, program tc6cr figure 13-7 16-bit pwm mode timing chart (tc5 and tc6) TMP88FW45AFG 13. 8-bit timercounter 5,6(tc5, 6) 13.3 function page 132 1 0 an an+1 ffff 0 an an+1 ffff 0 1 bm bm+1 ffff 0 bm cp b c 1 1 cp n a an ? ? ? internal source clock 16-bit shift register shift shift shift shift counter match detect match detect one cycle period match detect match detect an bm cp an m p tc6cr 13.3.8 16-bit programmable pulse generate (ppg) output mode (tc5 and 6) this mode is used to generate pulses with up to 16-bits of resolution. the timer counter 5 and 6 are cascadable to enter the 16-bit ppg mode. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg5, pwreg6) value is detected, the logic level output from the timer f/f6 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f6 is switched to the opposite state again when a match between the up-counter and the timer register (ttreg5, ttreg6) value is detected, and the counter is cleared. the inttc6 interrupt is generated at this time. since the initial value can be set to the timer f/f6 by tc6cr figure 13-8 16-bit ppg mode timing chart (tc5 and tc60) TMP88FW45AFG 13. 8-bit timercounter 5,6(tc5, 6) 13.3 function page 134 1 0 mn mn+1 qr-1 mn qr-1 1 mn mn+1 mn+1 0 qr 0 qr 1 0 internal source clock counter write of "0" match detect match detect match detect mn mn mn match detect match detect ? n m ? ? r q ? held at the level when the timer stops f/f clear tc6cr 14. motor control circuit (pmd: programmable motor driver) the TMP88FW45AFG contains two channels of motor control circuits used for sinusoidal waveform output. this motor control circuit can control brushless dc motors or ac motors with or without sensors. with its primary functions like those listed below incorporated in hardware, it helps to accomplish sine wave motor control easily, with the software load significantly reduced. 1. rotor position detect function ? can detect the rotor position, with or without sensors ? can be set to determine the rotor position when detection matched a number of times, to prevent erroneous detection ? can set a position detection inhibit period immediately after pwm-on 2. independent timer and timer capture functions for motor control ? contains one-channel magnitude comparison timer and two-channel coincidence comparison timers that operate synchronously for position detection 3. pwm waveform generating function ? generates 12-bit pwm with 100 ns resolution ? can set a frequency of pwm interrupt occurrence ? can set the dead time at pwm-on 4. protective function ? provides overload protective function based on protection signal input 5. emergency stop function in case of failure ? can be made to stop in an emergency by emg input or timer overflow interrupt ? not easily cleared by software runaway 6. auto commutation/auto position detection start function ? comprised of dual-buffers, can activate auto commutation synchronously with position detection or timer ? can set a position detection period using the timer function and start auto position detection at the set time 7. electrical angle timer function ? can count 360 degrees of electrical angle with a set period in the range of 0 to 383 ? can output the counted electrical angle to the waveform arithmetic circuit 8. waveform arithmetic circuit ? calculate the output duty cycle from the sine wave data and voltage data which are read from the ram based on the electrical angle timer ? output the calculation result to the waveform synthesis circuit TMP88FW45AFG page 135 14.1 outline of motor control the following explains the method for controlling a brushless dc motor with sine wave drive. in a brushless dc motor, the rotor windings to which to apply electric current are determined from the rotors magnetic pole position, and the current-applied windings are changed as the rotor turns. the rotors magnetic pole position is determined using a sensor such as a hall ic or by detecting polarity change (zero-cross) points of the induced voltage that develops in the motor windings (sensorless control). for the sensorless case, the induced voltage is detected by applying electric current to two phases and not applying electric current to the remaining other phase. in this two-phase current on case, there are six current application patterns as shown in table 14-1, which are changed synchronously with the phases of the rotor. in this two-phase current on case, the current on time in each phase is 120 degrees relative to 180 degrees of the induced voltage. table 14-1 current application patterns current application pattern upper transistor lower transistor current on winding u v w x y z mode 0 on off off off on off uv mode 1 on off off off off on uw mode 2 off on off off off on vw mode 3 off on off on off off vu mode 4 off off on on off off wu mode 5 off off on off on off wv note:one of the upper or lower transistors is pwm controlled. for brushless dc motors, the number of revolutions is controlled by an applied voltage, and the voltage application is controlled by pwm. at this time, the current on windings need to be changed in synchronism with the phases of the voltage induced by revolutions. control timing in cases where the current on windings are changed by means of sensorless control is illustrated in figure 14-4. for three-phase motors, zero-crossing occurs six times during one cycle of the induced voltage (electrical angle 360 degrees), so that the electrical angle from one zero-cross point to the next is 60 degrees. assuming that this period comprises one mode, the rotor position can be divided into six modes by zero- cross points. the six current application patterns shown above correspond one for one to these six modes. the timing at which the current application patterns are changed (commutation) is out of phase by 30 degrees of electrical angle, with respect to the position detection by an induced voltage. mode time is obtained by detecting a zero-cross point at some timing and finding an elapsed time from the preceding zero-cross point. because mode time corresponds to 60 degrees of electrical angle, the following applies for the case illustrated in figure 14-4. 1. current on windings changeover (commutation) timing 30 degrees of electrical angle = mode time/2 2. position detection start timing 45 degrees of electrical angle = mode time 3/4 3. failure determination timing 120 degrees of electrical angle = mode time 2 timings are calculated in this way. the position detection start timing in 2 is needed to prevent erroneous detection of the induced voltage for reasons that even after current application is turned off, the current continues flowing due to the motor reactance. control is exercised by calculating the above timings successively for each of the zero-cross points detected six times during 360 degrees of electrical angle and activating commutation, position detection start, and other operations according to that timing. in this way, operations can be synchronized to the phases of the induced voltage of the motor. the timing needed for motor control as in this example can be set freely as desired by using the internal timers of the microcontrollers pmd unit. TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.1 outline of motor control page 136 also, sine wave control requires controlling the pwm duty cycle for each pulse. control of pwm duty cycles is accomplished by counting degrees of electrical angle and calculating the sine wave data and voltage data at the counted degree of electrical angle. figure 14-1 conceptual diagram of dc motor control figure 14-2 example of sensorless dc motor control timing chart TMP88FW45AFG page 137 ! " # $%&'( #%$ '( &$ )$ ! "# $ $ $ %$ & '& $$ ( $ $ % ) & 14.2 configuration of the motor control circuit the motor control circuit consists of various units. these include a position detection unit to detect the zero-cross points of the induced voltage or position sensor signal, a timer unit to generate events at three instances of electrical angle timing, and a three-phase pwm output unit to produce three-phase output pwm waveforms. also included are an electrical angle timer unit to count degrees of electrical angle and a waveform arithmetic unit to calculate sinusoidal waveform output duty cycles. the input/output units are configured as shown in the diagram below. when using ports for the pmd function, set the port input/output control register (p3cri and p5cri) to 0 for the input ports, and for the output ports, set the data output latch (p3i and p5i) to 1 and then the port input/output control register to 1. other input/output ports can be set in the same way for use of the pmd function. figure 14-3 block diagram of the motor control circuit note 1: always use the ldw instruction to set data in the 9, 12 and 16-bit data registers. note 2: the emg circuit initially is enabled. for pmd output, fix the emg input port (p36 and p51) "h" high level or disable the emg circuit before using for pmd output. note 3: the emg circuit initially is enabled. when using port p3 and p5 as input/output io ports, disable emg. note 4: when going to stop mode, be sure to turn all of the pmd functions off before entering stop mode. TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.2 configuration of the motor control circuit page 138 ! 14.3 position detection unit the position detection unit identifies the motor's rotor position from input patterns on the position signal input port. applied to this position signal input port is the voltage status of the motor windings for the case of sensorless dc motors or a hall element signal for the case of dc motors with sensors included. the expected patterns corre- sponding to specific rotor positions are set in the pmd output register (mdout) beforehand, and when the input position signal and the expected value match as the rotation, a position detection interrupt (intpdc) is generated. also, unmatch detection mode is used to detect the direction of motor rotation, where when the status of the position detection input port changes from the status in which it was at start of sampling, a position detection interrupt is generated. for three-phase brushless dc motors, there are six patterns of position signals, one for each mode, as summarized in table 14-2 from the timing chart in figure 14-2. once a predicted position signal pattern is set in the mdout register, a position detection interrupt is generated the moment the position signal input port goes to mode indicated by this expected value. the position signals at each phase in the diagram are internal signals which cannot be observed from the outside. table 14-2 position signal input patterns position detection mode u phase (pdu) v phase (pdv) w phase (pdw) mode 0 h l h mode 1 h l l mode 2 h h l mode 3 l h l mode 4 l h h mode 5 l l h TMP88FW45AFG page 139 14.3.1 configuration of the position detection unit figure 14-4 configuration of the position detection circuit ? the position detection unit is controlled by the position detection control register (pdcra, pdcrb). after the position detection function is enabled, the unit starts sampling the position detection port with timer 2 or in software. for the case of ordinary mode, when the status of the position detection input port matches the expected value of the pmd output register, the unit generates a position detection interrupt and finishes sampling, waiting for start of the next sampling. ? when unmatch detection mode is selected for position detection, the unit stores the sampled status of the position detection port in memory at the time it started sampling. when the port input status changes from the status in which it was at start of sampling, an interrupt is generated. ? in unmatch detection mode, the port status at start of sampling can be read (pdcrc ! " ! !# # $ ## % & $ # & & ' & ( & & )& ( '* +,+-+ +%+ +.+/ / 0 . % 1+ ,+ -+ 2 %+ + .+ / -+ 1+ , '+ + !# ? a sampling delay is provided for use in modes where sampling is made while pwm is on or the lower phases are conducting current. it helps to prevent erroneous detection due to noise that occurs imme- diately after the transistor turns on, by starting sampling a set time after the pwm signal turned on. ? when detecting position while pwm is on or the lower phases are conducting current, a method can be selected whether to recount occurrences of matched position detection after being compared for each pwm signal on (logical sum of three-phase pwm signals) (e.g., starting from 0 in each pwm cycle) or counting occurrences of matching continuously ( pdcrb figure 14-5 position detection sampling timing with the pwmon period selected figure 14-6 detection timing of the position detection position TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.3 position detection unit page 142 ! "# % & " '( ) ) ) ) ) )) ) '** $ & " +, $ # )) ) ) !"# $ $#% & "# & "# "' & "# position detection circuit registers [addresses (pmd1 and pmd2)] pdcrc (01fa2h) (01fd2h) 7 6 5 4 3 2 1 0 - - emem smon pdtct (initial value: **00 0000) 5, 4 emem hold result of position detection at pwm edge (detect position detected position) 00: detected in the current pulse 01: detected while pwm off 10: detected in the current pulse 11: detected in the preceding pulse r 3 smon monitor sampling status 0: sampling idle 1: sampling in progress 2 to 0 pdtct hold position signal input status holds the status of the position signal input during unmatch detection mode. bits 2 to 0 correspond to w, v, and u phases. pdcrb (01fa1h) (01fd1h) 7 6 5 4 3 2 1 0 splck splmd pdcmp (initial value: 0000 0000) 7, 6 splck select sampling input clock 00: fc/2 2 [hz] (200 ns at 20 mhz) 01: fc/2 3 (400 ns at 20 mhz) 10: fc/2 4 (800 ns at 20 mhz) 11: fc/2 5 (1.6 s at 20 mhz) r/w 5, 4 splmd sampling mode 00: sample when pwm is on 01: sample regularly 10: sample when lower phases conducting current 11: reserved 3 to 0 pdcmp position detection matched counts 1 to 15 times (counts 0 and 1 are assumed to be one time.) note:when changing setting, keep the pdcen bit reset to 0 (disable position detection function). pdcra (01fa0h) (01fd0h) 7 6 5 4 3 2 1 0 swstp swstt sptm3 sttm2 pdnum rcen dtmd pdcen (initial value: 0000 0000) 7 swstp stop sampling in software 0: no operation 1: stop sampling w 6 swstt start sampling in software 0: no operation 1: start sampling 5 sptm3 stop sampling using timer 3 0: disable 1: enable r/w 4 sttm2 start sampling using timer 2 0: disable 1: enable 3 pdnum number of position signal input pins 0: compare three pins (pdu/pdv/pdw) 1: compare one pin (pdu) only 2 rcen recount occurrences of match- ing when pwm is on 0: continue counting from previously pwm on 1: recount each time pwm turns on 1 dtmd position detection mode 0: ordinary mode 1: unmatch detection mode 0 pdcen enable/disable position detec- tion function 0: disable 1: enable (sampling starts) TMP88FW45AFG page 143 note:read-modify-write instructions, such as a bit manipulation instruction, cannot access the pdcra because it contains a write only bit. TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.3 position detection unit page 144 sdreg (01fa3h) (01fd3h) 7 6 5 4 3 2 1 0 - d6 d5 d4 d3 d2 d1 d0 (initial value: *000 0000) 6 to 0 sdreg sampling delay 2 3 /fc n bits (n = 0 to 6, maximum 50.8 s, resolution of 400 ns at 20 mhz) r/w note:when changing setting, keep the pdcen bit reset to 0 (disable position detection function). 14.3.3 outline processing in the position detection unit TMP88FW45AFG page 145 ! "# $ % % !& ' ( ) ! 14.4 timer unit figure 14-7 timer circuit configuration the timer unit has an up counter (mode timer) which is cleared by a position detection interrupt (intpdc). using this counter, it can generate three types of timer interrupts (inttmr1 to 3). these timer interrupts may be used to produce a commutation trigger, position detection start trigger, etc. also, the mode timer has a capture function which automatically captures register data in synchronism with position detection or overload protection. this capture func- tion allows motor revolutions to be calculated by measuring position detection intervals. TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.4 timer unit page 146 !"# !" " $ % !"# "# %& ' ()*)+ ) ) ) , + ) ) ( - .' / / .' .' , .' 14.4.1 configuration of the timer unit the timer unit consists mainly of a mode timer, three timer comparator, and mode capture register, and is controlled by timer control registers and timer compare registers. ? the mode timer can be reset by a signal from the position detection circuit, timer 3, or overload protective circuit. if the mode timer overflows without being reset, it stops at ffffh and sets an overflow flag in the control register. ? the value of the mode timer during counting can be read by capturing the count in software and reading the capture register. ? timer 1 and timers 2 and 3 generate an interrupt signal by magnitude comparison and matching com- parison, respectively. therefore, timer 1 can generate an interrupt signal even when it could not write to the compare register in time and the counter value at the time of writing happens to exceed the registers set value. ? when any one of timers 1 to 3 interrupts occurs, the next interrupts can be enabled by writing a new value to the respective compare registers (cmp1, cmp2, cmp3). ? when capturing by position detection is enabled, the capture register has the timer value captured in it each time position is detected. in this way, the capture register always holds the latest value. TMP88FW45AFG page 147 14.4.1.1 timer circuit register functions mtcrb 7 dbout debug output debug output can be produced by setting this bit to 1. because interrupt signals to the interrupt control circuit are used for each interrupt, hardware debugging without software delays are possible. see the debug output diagram ( figure 14-8). output ports: p67 for pmd1, p77 for pmd2. 5 tmof mode timer overflow this bit shows that the timer has overflowed. 3 clcp capture mode timer by over- load protection when this bit is set to 1, the timer value can be captured using the overload protection signal (cl) as a trigger. 2 swcp capture mode timer in soft- ware when this bit is set to 1, the timer value can be captured in software (e.g., by writing to this register). 1 pdccp capture mode timer by posi- tion detection when this bit is set to 1, the timer value can be captured using the position detection signal as a trigger. mtcra 7, 6, 5 tmck select clock select the timer clock. 4 rbtm3 reset mode timer from timer 3 when this bit is set to 1, the mode timer is reset by a trigger from timer 3. 3 rbcl reset mode timer by overload protection when this bit is set to 1, the mode timer is reset by the overload protection signal (cl) as a trigger. 2 swres reset mode timer in software when this bit is set to 1, the mode timer is reset in software (e.g., by writing to this register) 1 rbpdc reset mode timer by position detection when this bit is set to 1, the mode timer is reset by the position detection signal as a trigger. 0 tmen enable/disable mode timer the mode timer is started by setting this bit to 1. therefore, timers 1 to 3 must be set with cmp before setting this bit. if this bit is set to 0 after setting cmp, cmp settings become ineffective. mcap mode capture position detection interval can be read out. cmp1 timer 1 (commutation) timers 1 to 3 are enabled while the mode timer is operating. an interrupt can be generated once by setting the corresponding bit in this register. the interrupt is disable when an in- terrupt is generated or the timer is reset. to use the timer again, set the register back again even if data is same. cmp2 timer 2 (position detection start) cmp3 timer 3 (overflow) figure 14-8 dbout debug output diagram TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.4 timer unit page 148 timer circuit registers [addresses (pmd1 and pmd2)] mtcrb (01fa5h) (01fd5h) 7 6 5 4 3 2 1 0 dbout - tmof - clcp swcp pdccp - (initial value: 0*0*0 000*) 7 dbout debug output 0: disable 1: enable (p67 for pmd1, p77 for pmd2) r/w 5 tmof mode timer overflow 0: no overflow 1: overflowed r 3 clcp capture mode timer by overload protection 0: disable 1: enable r/w 2 swcp capture mode timer in software 0: no operation 1: capture w 1 pdccp capture mode timer by position detection 0: disable 1: enable r/w note:read-modify-write instructions, such as a bit manipulation instruction, cannot access the mtcrb because it contains a write-only bit. mtcra (01fa4h) (01fd4h) 7 6 5 4 3 2 1 0 tmck rbtm3 rbcl swres rbpdc tmen (initial value: 0000 0000) 7, 6, 5 tmck select clock 000: fc/2 3 (400 ns at 20 mhz) 010: fc/2 4 (800 ns at 20 mhz) 100: fc/2 5 (1.6 s at 20 mhz) 110: fc/2 6 (3.2 s at 20 mhz) 001: fc/2 7 (6.4 s at 20 mhz) 011: reserved 101: reserved 111: reserved r/w 4 rbtm3 reset mode timer from timer 3 0: disable 1: enable 3 rbcl reset mode timer by overload protection 0: disable 1: enable 2 swres reset mode timer in software 0: no operation 1: reset w 1 rbpdc reset mode timer by position detection 0: disable 1: enable r/w 0 tmen enable/disable mode timer 0: disable 1: enable timer start note 1: when changing mtcra mcap (01fa7h, 01fa6h) (01fd7h, 01fd6h) f e d c b a 9 8 7 6 5 4 3 2 1 0 (initial value: 0000 0000 0000 0000) df de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mcap mode capture position detection interval r cmp1 (01fa9h, 01fa8h) (01fd9h, 01fd8h) f e d c b a 9 8 7 6 5 4 3 2 1 0 (initial value: 0000 0000 0000 0000) df de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cmp2 (01fabh, 01faah) (01fdbh, 01fdah) f e d c b a 9 8 7 6 5 4 3 2 1 0 (initial value: 0000 0000 0000 0000) df de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cmp3 (01fadh, 01fach) (01fddh, 01fdch) f e d c b a 9 8 7 6 5 4 3 2 1 0 (initial value: 0000 0000 0000 0000) df de dd dc db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cmp1 timer 1 magnitude comparison compare register r/w cmp2 timer 2 matching comparison compare register cmp3 timer 3 matching comparison compare register note:read-modify-write instructions, such as a bit manipulation instruction, cannot access the mtcrb or mtcra register because these registers contain write-only bits. TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.4 timer unit page 150 14.4.1.2 outline processing in the timer unit TMP88FW45AFG page 151 ! " " " # # $ % $ & ' '( ) ) ) ) * ) * $ $ + 14.5 three-phase pwm output unit the three-phase pwm output unit has the function to generate three-phase pwm waves with any desired pulse width and the commutation function capable of brushless dc motor control. in addition, it has the protective functions such as overload protection and emergency stop functions necessary to protect the power drive unit, and the dead time adding function which helps to prevent the in-phase upper/lower transistors from getting shorted by simultaneous turn- on when switched over. for the pwm output pin (u,v,w,x,y,z), set the port register pxdr and pxcr (x = 3,5) to 1. the pwm output initially is set to be active low, so that if the output needs to be used active high, set up the mdcra register accord- ingly. 14.5.1 configuration of the three-phase pwm output unit the three-phase pwm output unit consists of a pulse width modulation circuit, commutation control circuit, protective circuit (emergency stop and overload), and a dead time control circuit. 14.5.1.1 pulse width modulation circuit (pwm waveform generating unit) this circuit produces three-phase independent pwm waveforms with an equal pwm frequency. for pwm waveform mode, triangular wave modulation or sawtooth wave modulation can be selected by using the pmd control register (mdcra) bit 1. the pwm frequency is set by using the pmd period register (mdprd). the following shows the relationship between the value of this register and the pwm counter clock set by the mdcrb register, pwmck. the pmd period register (mdprd) is comprised of dual-buffers, so that cmpu, v, w register is updated with pwm period. when the waveform arithmetic circuit is operating, the pwm waveform output unit receives calculation results from the waveform arithmetic circuit and by using the results as cmpu, v, w register set value, it outputs independent three-phase pwm waveforms. when the waveform calculation function is enabled by the waveform arithmetic circuit and transfer of calculation results into the cmpu to w registers is enabled (with edcra register bit 2), the cmpu to w registers are disabled against writing. when the waveform calculation function is enabled (with edcra register bit 1) and transfer of calculation results into the cmpu, v, w registers is disabled (with edcra register bit 4), the calculation results are transferred to the buffers of cmpu, v, w registers, but not output to the port. read-accessing the cmpu, v, and w registers can read the calculation results of the waveform arithmetic circuit that have been input to a buffer. after changing the read calculation result data by software, writing the changed data to the cmpu, v, and w registers enables an arbitrary waveform other than a sinusoidal wave to be output. when the registers are read after writing, the values written to the registers are read out if accessed before the calculation results are transferred after calculation is finished. TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.5 three-phase pwm output unit page 152 figure 14-9 pwm waveforms the values of the pwm compare registers (cmpu/v/w) and the carrier wave generated by the pwm counter (mdcnt) are compared for the relative magnitude by the comparator to produce pwm waveforms. the pwm counter is a 12-bit up/down counter with a 100 ns (at fc = 20 mhz) resolution. for three-phase output control, two methods of generating three-phase pwm waveforms can be set. 1. three-phase independent mode: values are set independently in the three-phase pmd compare registers to produce three-phase independent pwm waveforms. this method may be used to produce sinusoidal or any other desired drive waveforms. 2. three-phase common mode: a value is set in only the u-phase pmd compare register to produce three in-phase pwm waveforms using the u phase set value. this method may be used for dc motor square wave drive. the three-phase pmd compare registers each have a comparison register to comprise a dual-buffer struc- ture. the values of the pmd compare registers are loaded into their respective comparison registers synchronously with pwm period. TMP88FW45AFG page 153 14.5.1.2 commutation control circuit output ports are controlled depending on the contents set in the pmd output register (mdout). the contents set in this register are divided into two, one for selecting the synchronizing signal for port output, and one for setting up port output. the synchronizing signal can be selected from timers 1 or 2, position detection signal, or without sync. port output can be synchronized to this synchronizing signal before being further synchronized to the pwm signal sync. the mdout register's synchronizing signal select bit becomes effective immediately after writing. other bits are dual-buffered, and are updated by the selected synchro- nizing signal. example: commutation timing for one timer period with pwm synchronization specified output on six ports can be set to be active high or active low independently of each other by using the mdcra register bits 5 and 4. furthermore, the u, v, and w phases can individually be selected between pwm output and h/l output by using the mdout register bits a to 8 and 5 to 0. when pwm output is selected, pwm waveforms are output; when h/l output is selected, a waveform which is fixed high or low is output. the mdout register bits e to c set the expected position signal value for the position detection circuit. figure 14-10 pulse width modulation circuit TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.5 three-phase pwm output unit page 154 3 selector/ latch pwm control pwm interrupt intpwm clock selector pmd period register pmd compare register pwm counter pwm control register ? ? 3, 2, 1 7 60 mdcra b to 0 mdprd b to 0 mdcnt 1 to 0 mdcrb b to 0 cmpu b to 0 cmpw b to 0 cmpv buffer w buffer v buffer u selector/ latch three-phase common/ three-phase up/down pwmu pwmv pwmw stop mdcnt pwm synchronizing clock fc/2 inttmr pwm commutation figure 14-11 commutation control circuit figure 14-12 dead time circuit TMP88FW45AFG page 155 ! " #$% & ' ($ ) )')&)*)+),)- s selector s selector gate control set reset latch 6 3 2 mdout 5, 4, 3, 2, 1, 0 a, 9, 87, 6 ? b ? , ? , ? mdout sync fc/4 pwm synchronizing clock position detection interrupt intpdc timer 1 interrupt inttmr1 timer 2 interrupt inttmr2 pmd output register u x v y w z pwmu pwmv pwmw 14.5.2 register functions of the waveform synthesis circuit mdcrb pwmck select pwm counter clock select pwm counter clock. TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.5 three-phase pwm output unit page 156 mdcra 7 hlfint select half-period interrupt when this bit is set to 1, intpwm is generated every half period (at triangular wave peak and valley) in the case of center pwm output and pint = 00. in other cases, this setting has no meaning. 6 dtymd duty mode select whether to set the duty cycle independently for three phases using the cmpu to w registers or in common for all three phases by setting the cmpu register only. 5 polh upper-phase port polarity select the upper-phase output port polarity. make sure the waveform synthesis function (mdcra register bit 0) is idle before selecting this port polarity. 4 poll lower-phase port polarity select the lower-phase output port polarity. make sure the waveform synthesis function (mdcra register bit 0) is idle before selecting this port polarity. 3, 2 pint pwm interrupt frequency select the frequency at which to generate a pwm interrupt from four choices available: every pwm period or once every 2, 4, or 8 pwm periods. when setting of this bit is altered while operating, an interrupt may be generated at the time the bit is altered. 1 pwmmd pwm mode select pwm mode. pwm mode 0 is an edge pwm (sawtooth wave), and pwm mode 1 is a center pwm (triangular wave). 0 pwmen enable/disable waveform generation circuit when enabling this circuit (for waveform output), be sure to set the output port polarity and other bits of this register (other than mdcra bit 0) beforehand. dtr dtr dead time set the dead time between the upper-phase and lower-phase outputs. mdout f updwn pwm counter flag this bit indicates whether the pwm counter is counting up or down. when edge pwm (sawtooth wave) is selected, it is always set to 0. e, d, c pdexp mode compare register set the data to be compared with the position detection input port. the comparison data is adopted as the expected value simultaneously when port output sync settings made with mdout are reflected in the ports. (this is the expected position detection input value for the output set with mdout next time.) b psync select pwm synchronization select whether or not to synchronize port output to pwm period after being synchronized to the synchronizing signal selected with syncs. if selected to be synchronized to pwm, output is kept waiting for the next pwm after being synchronized with syncs. waveform settings are overwritten if new settings are written to the register during this time, and output is generated with those settings. a 9 8 wpwm vpwm upwm control uvw-phase pwm outputs set u, v, and w-phase port outputs. (see the table 14-3) 7, 6 syncs select port output sync signal select the synchronizing signal with which to output uvw-phase settings to ports. the synchronizing signal can be selected from timers 1 or 2, position detection, or asynchro- nous. select asynchronous when the initial setting, otherwise the above setting isnt reflected immediately. 5, 4 3, 2 1, 0 woc voc uoc control uvw-phase outputs set u, v, and w-phase port outputs. (see the table 14-3) mdcnt pwm counter this is a 12-bit read-only register used to count pwm periods. mdprd set pwm period this register determines pwm period, and is dual-buffered, allowing pwm period to be altered even while the pwm counter is operating. the buffers are loaded every pwm pe- riod. when 100 ns is selected for the pwm counter clock, make sure the least significant bit is set to 0. cmpu cmpv cmpw set pwm pulse width this comparison register determines the pulse widths output in the respective uvw pha- ses. this register is dual-buffered, and the pulse widths are determined by comparing the buffer and pwm counter. TMP88FW45AFG page 157 waveform synthesis circuit registers [addresses (pmd1 and pmd2)] mdcrb (01fafh) (01fdfh) 7 6 5 4 3 2 1 0 - - - - - - pwmck (initial value: **** **00) 1, 0 pwmck pwm counter select clock 00: fc/2 [hz] (100 ns at 20 mhz) 01: fc/2 2 (200 ns at 20 mhz) 10: fc/2 3 (400 ns at 20 mhz) 11: fc/2 4 (800 ns at 20 mhz) r/w note:when changing setting, keep the pwmen bit reset to 0 (disable wave form synthesis function). mdcra (01faeh) (01fdeh) 7 6 5 4 3 2 1 0 hlfint dtymd polh poll pint pwmmd pwmen (initial value: 0000 0000) 7 hlfint select half-period interrupt 0: interrupt as specified in pint 1: interrupt every half period when pint = 00 r/w 6 dtymd duty mode 0: u phase in common 1: three phases independent 5 polh upper-phase port polarity 0: active low 1: active high 4 poll lower-phase port polarity 0: active low 1: active high 3, 2 pint select pwm interrupt (trigger) 00: interrupt every period 01: interrupt once every 2 periods 10: interrupt once every 4 periods 11: interrupt once every 8 periods 1 pwmmd pwm mode 0: pwm mode0 (edge: sawtooth wave) 1: pwm mode1 (center: triangular wave) 0 pwmen enable/disable waveform syn- thesis function 0: disable 1: enable (waveform output) dtr (01fbeh) (01feeh) 7 6 5 4 3 2 1 0 - - d5 d4 d3 d2 d1 d0 (initial value: **00 0000) 5 to 0 dtr dead time 2 3 /fc 6 bit (maximum 25.2 s at 20 mhz) r/w note:when changing setting, keep the mdcra mdout (01fb3h, 01fb2h) (01fe3h, 01fe2h) f e d c b a 9 8 updwn pdexp psync wpwm vpwm upwm 7 6 5 4 3 2 1 0 syncs woc voc uoc (initial value: 00000000 00000000) f updwn pwm counter flag 0: counting up 1: counting down r e, d, c pdexp comparison register for position detection bit e: w-phase expected value bit d: v-phase expected value bit c: u-phase expected value r/w b psync select pwm synchronization 0: asynchronous 1: synchronized a wpwm w-phase pwm output 0: h/l level output 1: pwm waveform output 9 vpwm v-phase pwm output 0: h/l level output 1: pwm waveform output 8 upwm u-phase pwm output 0: h/l level output 1: pwm waveform output 7, 6 syncs select port output synchronizing signal 00: asynchronous 01: synchronized to position detection 10: synchronized to timer 1 11: synchronized to timer 2 5, 4 woc control w-phase output see the table 1-3 3, 2 voc control v-phase output 1, 0 uoc control u-phase output 14.5.3 port output as set with uoc/voc/woc bits and upwm/vpwm/wpwm bits table 14-3 example of pin output settings u-phase output polarity: active high (polh,poll = 1) u-phase output polarity: active low (polh,poll = 0) uoc upwm uoc upwm 1: pwm output 0: h/l level output 1: pwm output 0: h/l level output u phase x phase u phase x phase u phase x phase u phase x phase 0 0 pwm pwm l l 0 0 pwm pwm h h 0 1 l pwm l h 0 1 h pwm h l 1 0 pwm l h l 1 0 pwm h l h 1 1 pwm pwm h h 1 1 pwm pwm l l TMP88FW45AFG page 159 mdcnt (01fb5h, 01fb4h) (01fe5h, 01fe4h) f e d c b a 9 8 7 6 5 4 3 2 1 0 (initial value: ****000000000000) - - - - db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 b to 0 pwm counter pwm period counter value r mdprd (01fb7h, 01fb6h) (01fe7h, 01fe6h) f e d c b a 9 8 7 6 5 4 3 2 1 0 (initial value: ****000000000000) - - - - db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 b to 0 pwm period pwm period mdprd 010h r/w cmpu (01fb9h, 01fb8h) (01fe9h, 01fe8h) f e d c b a 9 8 7 6 5 4 3 2 1 0 (initial value: ****000000000000) - - - - db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cmpv (01fbbh, 01fbah) (01febh, 01feah) f e d c b a 9 8 7 6 5 4 3 2 1 0 (initial value: ****000000000000) - - - - db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cmpw (01fbdh, 01fbch) (01fedh, 01fech) f e d c b a 9 8 7 6 5 4 3 2 1 0 (initial value: ****000000000000) - - - - db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 b to 0 cmpu pwm compare u register set u-phase duty cycle r/w cmpv pwm compare v register set v-phase duty cycle cmpw pwm compare w register set w-phase duty cycle TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.5 three-phase pwm output unit page 160 14.5.4 protective circuit this circuit consists of an emg protective circuit and overload protective circuit. these circuits are activated by driving their respective port inputs active. figure 14-13 configuration of the protective circuit a. emg protective circuit this protective circuit is used for emergency stop, when the emg protective circuit is enabled. when the signal on emg input port goes active (negative edge triggered), the six ports are immediately disabled high-impedance against output and an emg interrupt (intemg) is generated. the emg control register (emgcra) is used to set emg protection. if the emgcra the number of times the overload protective input is sampled can be set by using the emg- cra ! 14.5.5 functions of protective circuit registers emgrel emg disable the emg protective circuit is disable from the disabled state by writing 5ah and a5h to this register in that order. after that, the emgcra register needs to be set. emgcrb 7 rtcl return from overload protec- tive state when this bit is set to 1, the motor control circuit is returned from overload protective state in software (e.g., by writing to this register). also, the current state can be known by reading this bit. mdout outputs at return from the overload protective state remain as set before the overload protective input was driven active. 6 rtpwm return by pwm sync when this bit is set to 1, the motor control circuit is returned from overload protective state by pwm sync. if rtcl is set to 1, rtcl has priority. 5 rttm1 return by timer sync when this bit is set to 1, the motor control circuit is returned from overload protective state by timer 1 sync. if rtcl is set to 1, rtcl has priority. 4 clst overload protective state the status of overload protection can be known by reading this bit. 3, 2 clmd select output disabled phases during overload protection select the phases to be disabled against output during overload protection. this facility allows selecting to disable no phases, all phases, pwm phases, or all upper phases/all lower phases. 1 cntst stop counter during overload protection can stop the pwm counter during overload protection. 0 clen enable/disable overload pro- tection enable or disable the overload protective function. emgcra 7 to 4 clcnt overload protection sampling time set the length of time the overload protective input port is sampled. 2 emgst emg protective state the status of emg protection can be known by reading this bit. 1 rte return from emg protective state the motor control circuit is returned from emg protective state by setting this bit to 1 . when returning, set the mdout register a to 0 bits to 0 . then set the emgcra register bit 1 to 1 and set mdout waveform output. then set up the mdcra register. 0 emgen enable/disable emg protec- tive circuit the emg protective circuit is activated by setting this bit to 1. this circuit initially is enabled. (to disable this circuit, make sure key code 5ah and a5h are written to the emgrel1 register beforehand.) protective circuit registers [addresses (pmd1 and pmd2)] emgrel (01fbfh) (01fefh) 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 (initial value: 0000 0000) 7 to 0 emgrel emg disable can disable by writing 5ah and then a5h. w note:read-modify-write instructions, such as a bit manipulation instruction, cannot access the emgrel register be- cause this register is write only. TMP88FW45AFG page 163 emgcrb (01fb1h) (01fe1h) 7 6 5 4 3 2 1 0 rtcl rtpwm rttm1 clst clmd cntst clen (initial value: 0000 0000) 7 rtcl return from overload protective state 0: no operation 1: return from protective state w 6 rtpwm enable/disable return from overload protective state by pwm sync 0: disable 1: enable r/w 5 rttm1 enable/disable return from overload protective state by tim- er 1 0: disable 1: enable 4 clst overload protective state 0: no operation 1: under protection r 3, 2 clmd select output disabled phases during overload protection 00: no phases disabled against output 01: all phases disabled against output 10: pwm phases disabled against output 11: all upper/all lower phases disabled against output (note) r/w 1 cntst stop pwm counter during over- load protection 0: do not stop 1: stop the counter 0 clen enable/disable overload pro- tective circuit 0: disable 1: enable note:if during overload protection the port output state in two or more upper phases is on, all lower phases are disabled and all upper phases are enabled for output; when two or more lower phases are on, all upper phases are disabled and all lower phases are enabled for output. emgcra (01fb0h) (01fe0h) 7 6 5 4 3 2 1 0 clcnt emgst rte emgen (initial value: 0000 *001) 7 to 4 clcnt overload protection sampling number of times. 2 2 /fc n ( n = 1 to 15, 0 and 1 are set as 1 at 20 mhz ) r/w 2 emgst emg protective state 0: no operation 1: under protection r 1 rte return from emg state 0: no operation 1: return from protective state (note 1) w 0 emgen enable/disable emg protective circuit 0: disable 1: enable r/w note 1: an instruction specifying a return from the emg state is invalid if the emg input is l. note 2: read-modify-write instructions, such as a bit manipulation instruction, cannot access the emgcrb or emgcra register because these registers contain write-only bits. TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.5 three-phase pwm output unit page 164 14.6 electrical angle timer and waveform arithmetic circuit electrical angle timer figure 14-15 electrical angle timer circuit waveform arithmetic circuit figure 14-16 waveform arithmetic circuit TMP88FW45AFG page 165 ! " # $%& ' $ ! " # % ( )*")( + , -)( .)( /)( %&. %&- %&/ ( 0122 # " ! /3%4 4$ # " 4' . 4$% "! 5 # " ! ! ! "! # $% !#!&!"!!'! !!( )* + ,( - - . - - 14.6.1 electrical angle timer and waveform arithmetic circuit the electrical angle timer finishes counting upon reaching the value set by the period set register (edset). the electrical angle timer counts 360 degrees of electrical angle in the range of 0 to 383 (17fh) and is cleared to 0 upon reaching 383. in this way, it is possible to obtain the electrical angle of the frequency proportional to the value set by the period set register. the period with which to count up can be corrected by using the period correction register, allowing for fine adjustment of the frequency. the electrical angles counted by the electrical angle timer are presented to the waveform arithmetic circuit. an electrical angle timer interrupt signal is generated each time the electrical angle timer finishes counting. the waveform arithmetic circuit has a sine wave data table, which is used to extract sine wave data based on the electrical angle data received from the electrical angle timer. this sine wave data is multiplied by the value of the voltage amplitude register. for 2-phase modulation, the product obtained by this multiplication is presented to the waveform synthesis circuit. for 3-phase modulation, waveform data is further calculated based on the product of multiplication and the electrical angle data and the value of the pwm period register. the calculation is performed each time the electrical angle timer finishes counting or when a value is set in the electrical angle register, and the calculation results consisting of the u phase, the v phase (+120 degrees), and the w phase (+240 degrees) are sequentially presented to the pwm waveform output circuit. the sine wave data table is stored in the ram and requires initialization. ? to correct the period, set the number of times n to be corrected in the period correction register (edset register f to c bits). the period is corrected by adding 1 to electrical angle counts 16 for n times. for example, when a value 3 is set in the period correction register, the period for 13 times out of electrical angle counts 16 is the value mh set in the period set register, and that for 3 times is m + 1h. (correction is made almost at equal intervals.) ? because the electrical angle counter (eldeg) can be accessed even while the electrical angle timer is operating, the electrical angles can be corrected during operation. ? the electrical angle capture edcap captures the electrical angle value from the electrical angle counter at the time the position is detected. ? when the waveform calculation function is enabled, waveform calculation is performed each time the electrical angle counter (eldeg) are accessed for write or the electrical angle timer finishes counting. ? the calculation is performed in 35 machine cycle of execution time, or 7 s (at 20 mhz). ? when transfer of calculation result to the cmp registers is enabled (edcra 14.6.1.1 functions of the electrical angle timer and waveform arithmetic circuit registers edcrb 3 calcst start calculation by software forcefully start calculation. when this bit is written while the waveform arithmetic circuit is calculating, the calculation is terminated and then newly started. 2 calcbsy calculation flag by reading this bit, the operation status of the waveform arithmetic circuit can be obtained. 1 edcalen enable/disable calculation start synchronized with elec- trical angle select whether to start calculation when the electrical angle timer finishes counting or when a value is set in the electrical angle register. when disabled, calculation is only started when calcst is set to 1. 0 edisel electrical angle interrupt set the electrical angle interrupt signal request timing to either when the electrical angle timer finishes counting or upon end of calculation. edcra 7 edcnt electrical angle count up/ down set whether the electrical angle timer counts up or down. 6 edrv select v-, w-phase select phase direction of v-phase and w-phase in relation to u-phase. 5, 4 edck select clock select the clock for the electrical angle timer. this setting can be altered even while the electrical angle timer is operating. 3 c2pen switch between 2-phase and 3-phase modulations select the modulation method with which to perform waveform calculation. two-phase modulation data = ramdata (eldeg) amp note: the sign during 3-phase modulation changes depending on the electrical angle. + for electrical angles 0 to 179 degrees (191) ? for electrical angles 180 (192) to 360 (383) degrees 2 rwren auto transfer calculation re- sults to cpm registers enable/disable transfer of calculation results by the waveform arithmetic circuit. when the waveform calculation function is enabled while at the same time transfer is enabled, cal- culation results are set as u, v, and w-phase duty cycles of the pwm generation circuit and are reflected in the ports. 1 calcen enable/disable waveform cal- culation function enable/disable the waveform calculation function. calculations are performed by the wave- form arithmetic circuit by enabling the waveform calculation function. when the waveform calculation function is enabled, the calculated results can be read from the u, v, and w- phase compare registers (cmpu, v, w) of the pwm generation circuit. 0 edten electrical angle timer enable/disable the electrical angle timer. when enabled, the electrical angle timer starts counting; when disabled, the electrical angle timer stops counting and is cleared to 0. edset f to c edth correct electrical angle period correct the period by adding 1 to electrical angle counts 16 for n times. the timer counts the electrical angle period set value mfor (16 ? n) times and counts (m + 1) for n times b to 0 edt electrical angle period set the electrical angle period. eldeg electrical angle read the electrical angle. this register can also be set to initialize or correct the angle while counting. any value greater than 17fh cannot be set. amp set voltage amplitude set the voltage amplitude. the waveform arithmetic circuit multiplies the data set here by the sine wave data read out from the sine wave ram. the amplitude has its upper limit determined by the set value of the mdprd register when performing this multiplication. edcap capture electrical angle capture the value from the electrical angle timer when the position is detected. wfmdr set sine wave data to initialize the entire ram data of the sine wave table, set the addresses at which to set, sequentially from 000h to 17fh, in the eldeg register, and write waveform data to the wfmdr register each time. make sure the waveform arithmetic circuit is disabled when writing this data. TMP88FW45AFG page 167 typical settings of sine wave data note:during 3-phase modulation, the sign changes at 180 degrees of electrical angle. figure 14-17 typical settings of sine wave data list of the electrical angle timer and waveform arithmetic circuit registers [addresses (pmd1 and pmd2)] edcrb (01fc1h) (01ff1h) 7 6 5 4 3 2 1 0 - - - - calcst calcbsy edcalen edisel (initial value: **** 0000) 3 calcst start calculation by software 0: no operation 1: start calculation w 2 calcbsy calculation flag 0: waveform arithmetic circuit stopped 1: waveform arithmetic circuit calculating r 1 edcalen enable/disable calculation start synchronized with electrical an- gle 0: start calculation insync with electrical angle 1: do not calculation insync with electrical angle r/w 0 edisel electrical angle interrupt 0: interrupt when the electrical angle timer finishes counting 1: interrupt upon end of calculation note:read-modify-write instructions, such as a bit manipulation instruction, cannot access the edcrb register be- cause this register is write only. TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.6 electrical angle timer and waveform arithmetic circuit page 168 ! ! ! ! ! "# "$ " % % ' ! ! ! ! ! "# "$ " % % ' edcra (01fc0h) (01ff0h) 7 6 5 4 3 2 1 0 edcnt edrv edck c2pen rwren calcen edten (initial value: 0000 0000) 7 edcnt electrical angle count up/down 0: count up 1: count down r/w 6 edrv select v-, w-phase 0: v = u + 120, w = u + 240 1: v = u ? 120, w = u ? 240 5, 4 edck select clock 00: fc/2 3 (400 ns at 20 mhz) 01: fc/2 4 (800 ns at 20 mhz) 10: fc/2 5 (1.6 s at 20 mhz) 11: fc/2 6 (3.2 s at 20 mhz) 3 c2pen switch between 2-/3-phase modulations 0: 2-phase modulation 1: 3-phase modulation 2 rwren transfer calculation result to cmp registers 0: disable 1: enable 1 calc enable/disable waveform cal- culation function 0: disable 1: enable 0 edten electrical angle enable/disable mode timer 0: disable 1: enable note:when changing the edcra eldeg (01fc5h, 01fc4h) (01ff5h, 01ff4h) f e d c b a 9 8 7 6 5 4 3 2 1 0 (initial value: *******0 00000000) - - - - - - - d8 d7 d6 d5 d4 d3 d2 d1 d0 8 to 0 eldeg electrical angle set the initially and the count values of electrical angle. r/w amp (01fc7h, 01fc6h) (01ff7h, 01ff6h) f e d c b a 9 8 7 6 5 4 3 2 1 0 (initial value: ****0000 00000000) - - - - db da d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 b to 0 amp set voltage set the voltage to be used during waveform calculation. r/w edcap (01fc9h, 01fc8h) (01ff9h, 01ff8h) f e d c b a 9 8 7 6 5 4 3 2 1 0 (initial value: ******0 00000000) - - - - - - - d8 d7 d6 d5 d4 d3 d2 d1 d0 8 to 0 edcap captured value of electrical an- gle electrical angle timer value when position is detected. r wfmdr (01fcah) (01ffah) 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 (initial value: ********) 7 to 0 wfmdr sine wave data write sine wave data to ram of sine wave w note:read-modify-write instructions, such as a bit manipulation instruction, cannot access the wfmdr register be- cause this register is write only. TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.6 electrical angle timer and waveform arithmetic circuit page 170 14.6.1.2 list of pmd related control registers (1) input/output pins and input/output control registers pmd1 input/output pins (p3, p4) and port input/output control registers (p3cr, p4cr) name address bit r or w description p3dr 00003h 7 r/w overload protection ( cl1) 6 r/w emg input ( emg1) 5 to 0 r/w u1/v1/w1/x1/y1/z1 outputs. p4dr 00004h 2 to 0 r/w position signal inputs (pdu1, pdv1, pdw1). p3cr 01f89h 7 to 0 r/w p3 port input/output control (can be set bitwise). 0: input mode 1: output mode p4cr 01f8ah 2, 1, 0 r/w p0 port input/output control (can be set bitwise). 0: input mode 1: output mode pmd2 input/output pins (p5, p1) and port input/output control registers (p5cr, p1cr) name address bit r or w description p5dr 00005h 0 r/w overload protection ( cl2) 1 r/w emg input ( emg2) 2 to 7 r/w u2/v2/w2/x2/y2/z2 outputs. p1dr 00001h 5 to 7 r/w position signal inputs (pdu2, pdv2, pdw2). p5cr 01f8bh 7 to 0 r/w p3 port input/output control (can be set bitwise). 0: input mode 1: output mode p1cr 0000bh 5, 6, 7 r/w p0 port input/output control (can be set bitwise). 0: input mode 1: output mode note:when using these pins as pmd function or input port, set the output latch (p*dr) to 1. example of the pmd pin port setting input/output p3dr p3cr p4dr p4cr cl1 input * 0 - - emg1 input * 0 - - u1 output 1 1 - - pdu1 input - - * 0 input/output p5dr p5cr p1dr p1cr cl2 input * 0 - - emg2 input * 0 - - u2 output 1 1 - - pdu2 input - - * 0 TMP88FW45AFG page 171 (2) motor control circuit control registers [address upper stage: pmd1, lower stage: pmd2] position detection control register (pdcr) and sampling delay register (sdreg) name address bit r or w description pdcrc 01fa2h 01fd2h 5, 4 r detect the position-detected position. 00: within the current pulse 01: when pwm is off 10: within the current pulse 11: within the preceding pulse 3 r monitor the sampling status. 0: sampling idle 1: sampling in progress 2 to 0 r holds the status of the position signal input during unmatch detection mode. bits 2, 1, and 0: w, v, and u phases pdcrb 01fa1h 01fd1h 7, 6 r/w select the sampling input clock [hz]. 00: fc/2 2 01: fc/2 3 10: fc/2 4 11: fc/2 5 5, 4 r/w sampling mode. 00: when pwm is on 01: regularly 10: when lower phases are turned on 3 to 0 r/w detection position match counts 1 to 15. pdcra 01fa0h 01fd0h 7 w 0: no operation 1: stop sampling in software 6 w 0: no operation 1: start sampling in software 5 r/w stop sampling using timer 3. 0: disable 1: enable 4 r/w start sampling using timer 2. 0: disable 1: enable 3 r/w number of position signal input pins. 0: compare three pins (pdu/pdv/pdw) 1: compare one pin (pdu) only 2 r/w count occurrences of matching when pwm is on. 0: subsequent to matching counts when pwm previously was on 1: recount occurrences of matching each time pwm is on 1 r/w position detection mode. 0: ordinary mode 1: unmatch detection mode 0 r/w enable/disable position detection function. 0: disable 1: enable (sampling starts) sdreg 01fa3h 01fd3h 6 to 0 r/w sampling delay. 2 3 /fc n bits (n = 0 to 6, maximum 50.8 s at 20 mhz). TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.6 electrical angle timer and waveform arithmetic circuit page 172 mode timer control register (mtcr), mode capture register (mcap), and compare registers (cmp1, cmp2, cmp3) name address bit r or w description mtcrb 01fa5h 01fd5h 7 r/w debug output. 0: disable 1: enable (p67 for pmd1, p77 for pmd2) 5 r mode timer overflow. 0: no overflow 1: overflowed occurred 3 r/w capture mode timer by overload protection. 0: disable 1: enable 2 w capture mode timer by software. 0: no operation 1: capture 1 r/w capture mode timer by position detection. 0: disable 1: enable mtcra 01fa4h 01fd4h 7, 6, 5 r/w select clock for mode timer [hz]. 000: fc/2 3 (400 ns at 20 mhz) 010: fc/2 4 (800 ns at 20 mhz) 100: fc/2 5 (1.6 s at 20 mhz) 110: fc/2 6 (3.2 s at 20 mhz) 001: fc/2 7 (6.4 s at 20 mhz) 011: reserved 101: reserved 111: reserved 4 r/w reset timer by timer 3. 0: disable 1: enable 3 r/w reset timer by overload protection. 0: disable 1: enable 2 w reset timer by software. 0: no operation 1: reset 1 r/w reset timer by position detection. 0: disable 1: enable 0 r/w enable/disable mode timer. 0: disable 1: enable (timer starts) mcap 01fa7h, 01fa6h 01fd7h, 01fd6h f to 0 r mode capture register. cmp1 01fa9h, 01fa8h 01fd9h, 01fd8h f to 0 r/w compare register 1. cmp2 01fabh, 01faah 01fdbh, 01fdah f to 0 r/w compare register 2. cmp3 01fadh, 01fach 01fddh, 01fdch f to 0 r/w compare register 3. TMP88FW45AFG page 173 pmd control register (mdcr), dead time register (dtr), and pmd output register (mdout) name address bit r or w description mdcrb 01fafh 01fdfh 1, 0 r/w select clock for pwm counter. 00: fc/2 (100 ns at 20 mhz) 01: fc/2 2 (200 ns at 20 mhz) 10: fc/2 3 (400 ns at 20 mhz) 11: fc/2 4 (800 ns at 20 mhz) mdcra 01faeh 01fdeh 7 r/w select half-period interrupt 0: interrupt every period as specified in pint. 1: interrupt every half-period only pint=00. 6 r/w duty mode. 0: u phase in common 1: three phases independent 5 r/w upper-phase port polarity. 0: active low 1: active high 4 r/w lower-phase port polarity. 0: active low 1: active high 3, 2 r/w select pwm interrupt (trigger). 00: interrupt once every period 01: interrupt once 2 periods 10: interrupt once 4 periods 11: interrupt once 8 periods 1 r/w pwm mode. 0: pwm mode0 (edge: sawtooth wave) 1: pwm mode1 (center: triangular wave) 0 r/w enable/disable waveform synthesis function. 0: disable 1: enable (waveform output) dtr 01fbeh 01feeh 5 to 0 r/w set dead time. 2 3 /fc 6bit (maximum 25.2 s at 20 mhz). mdout 01fb3h, 01fb2h 01fe3h, 01fe2h f r 0: count up 1: count down e, d, c r/w comparison register for position detection. 6: w 5: v 4: u b r/w select pwm synchronization. 0: asynchronous with pwm period 1: synchronized a r/w w-phase pwm output. 0: h/l level output 1: pwm waveform output 9 r/w v-phase pwm output. 0: h/l level output 1: pwm waveform output 8 r/w u-phase pwm output. 0: h/l level output 1: pwm waveform output 7, 6 r/w select port output synchronizing signal. 00: asynchronous 01: synchronized to position detection 10: synchronized to timer 1 11: synchronized to timer 2 5, 4 r/w control w-phase output 3, 2 r/w control v-phase output 1, 0 r/w control u-phase output TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.6 electrical angle timer and waveform arithmetic circuit page 174 pwm counter (mdcnt), pmd period register (mdprd), and pmd compare registers (cmpu, cmpv, cmpw) name address bit r or w description mdcnt 01fb5h, 01fb4h 01fe5h, 01fe4h b to 0 r read the pwm period counter value. mdprd 01fb7h, 01fb6h 01fe7h, 01fe6h b to 0 r/w pwm period mdprd 010h. cmpu 01fb9h, 01fb8h 01fe9h, 01fe8h b to 0 r/w set u-phase pwm duty cycle. cmpv 01fbbh, 01fbah 01febh, 01feah b to 0 r/w set v-phase pwm duty cycle. cmpw 01fbdh, 01fbch 01fedh, 01fech b to 0 r/w set w-phase pwm duty cycle. emg disable code register (emgrel) and emg control register (emgcr) TMP88FW45AFG page 175 name address bit r or w description emgrel 01fbfh 01fefh 7 to 0 w code input for disable emg protection circuit. can be disable by writing 5ah and then a5h. emgcrb 01fb1h 01fe1h 7 w return from overload protective state. 0: no operation 1: return from protective state 6 r/w condition for returning from overload protective state: synchronized to pwm. 0: disable 1: enable 5 r/w enable/disable return from overload protective state by timer 1. 0: disable 1: enable 4 r overload protective state. 0: no operation 1: under protection 3, 2 r/w select output disabled phases during overload protection. 00: no phases disabled against output 01: all phases disabled against output 10: pwm phases disabled against output 11: all upper/all lower phases disabled against output 1 r/w stop pwm counter (mdcnt) during overload protection. 0: do not stop 1: stop 0 r/w enable/disable overload protective circuit. 0: disable 1: enable emgcra 01fb0h 01fe0h 7 to 4 r/w overload protection sampling time. 2 2 /fc n (n = 1 to 15, at 20 mhz) 2 r emg protective state. 0: no operation 1: under protection 1 w return from emg protective state. 0: no operation 1: return from protective state 0 r/w enable/disable function of the emg protective circuit. 0: disable 1: enable (this circuit initially is enabled (= 1). to disable this circuit, make sure key code 5ah and a5h are written to the emgrel1 register before- hand.) TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.6 electrical angle timer and waveform arithmetic circuit page 176 electrical angle control register (edcr), electrical angle period register (edset), electrical angle set register (eldeg), voltage set register (amp), and electrical angle capture register (edcap). name address bit r or w description edcrb 01fc1h 01ff1h 3 w 0: no operation 1: start calculation 2 r 0: waveform arithmetic circuit stopped 1: waveform arithmetic circuit calculation 1 r/w 0: start calculation insync with electrical angle 1: do not calculation insync with electrical angle 0 r/w 0: interrupt when the electrical angle timer finishes counting 1: interrupt upon end of calculation edcra 01fc0h 01ff0h 7 r/w 0: count up 1: count down 6 r/w 0: v = u + 120, w = u + 240 1: v = u ? 120, w = u ? 240 5, 4 r/w select clock. 00: fc/2 3 01: fc/2 4 10: fc/2 5 11: fc/2 6 3 r/w switch between 2/3-phase modulations. 0: two-phase modulation 1: three-phase modulation 2 r/w transfer calculation result to cmp registers. 0: disable 1: enable 1 r/w enable/disable waveform calculation function. 0: disable 1: enable 0 r/w electrical angle timer. 0: disable 1: enable edset 01fc3h, 01fc2h 01ff3h, 01ff2h f to c r/w correct period (n) 0 to 15 times. b to 0 r/w set period (1/m counter) 010h eldeg 01fc5h, 01fc4h 01ff5h, 01ff4h 8 to 0 r/w initially set and count values of electrical angle. amp 01fc7h, 01fc6h 01ff7h, 01ff6h b to 0 r/w set voltage used during waveform calculation. edcap 01fc9h, 01fc8h 01ff9h, 01ff8h 8 to 0 r electrical angle timer value when position is detected. wfmdr 01fcah 01ffah 7 to 0 w set sine wave data. TMP88FW45AFG page 177 TMP88FW45AFG 14. motor control circuit (pmd: programmable motor driver) 14.6 electrical angle timer and waveform arithmetic circuit page 178 15. asynchronous serial interface (uart1) the TMP88FW45AFG has a asynchronous serial interface (uart) . it can connect the peripheral circuits through txd and rxd pin. txd and rxd pin are also used as the general port. for txd pin, the corresponding general port should be set output mode (set its output control register to "1" after its output port latch to "1"). for rxd pin, should be set input mode. the asynchronous serial interface (uart1) can select the connection pin with the peripheral circuits. rxd1 and txd1 are correspond to p44 and p45 pins, rxd2 and txd2 are to p00 and p01 pins. but the synchronous serial interface (sio) also use p44 and p45 pins, therefore these p44 and p45 are not available for uart when sio is on working. 15.1 configuration figure 15-1 uart1 (asynchronous serial interface) TMP88FW45AFG page 179 counter y a b c s s a b c d y e f g h uart status register uart control register 2 uart pin select register irda output control register uart control register 1 transmit data buffer receive data buffer fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 fc/96 stop bit parity bit fc/2 6 fc/2 7 fc/2 8 rxd1 rxd2 txd1 txd2 baud rate generator transmit/receive clock 2 4 3 2 2 2 noise rejection circuit irda control irdacr uartsel shift register transmit control circuit receive control circuit shift register m p x m p x m p x mpx: multiplexer uartcr1 tdbuf rdbuf inttxd intrxd uartsr uartcr2 inttc4 15.2 control uart1 is controlled by the uart1 control registers (uartcr1, uartcr2). the operating status can be monitored using the uart status register (uartsr). txd pin and rxd pin can be selected a port assignment by uart pin select register (uartsel). uart1 control register1 uartcr1 (01f91h) 7 6 5 4 3 2 1 0 txe rxe stbt even pe brg (initial value: 0000 0000) txe transfer operation 0: 1: disable enable write only rxe receive operation 0: 1: disable enable stbt transmit stop bit length 0: 1: 1 bit 2 bits even even-numbered parity 0: 1: odd-numbered parity even-numbered parity pe parity addition 0: 1: no parity parity brg transmit clock select 000: 001: 010: 011: 100: 101: 110: 111: fc/13 [hz] fc/26 fc/52 fc/104 fc/208 fc/416 input inttc4 fc/96 note 1: when operations are disabled by setting uartcr1 brg setting transfer clock [hz] rxdnc setting 00 (no noise rejection) 01 (reject pulses shorter than 31/fc[s] as noise) 10 (reject pulses shorter than 63/fc[s] as noise) 11 (reject pulses shorter than 127/fc[s] as noise) 000 fc/13 - 110 (when the transfer clock gen- erated by timer/counter inter- rupt is the same as the right side column) fc/8 - - - fc/16 - - fc/32 - the setting except the above uart1 status register uartsr (01f91h) 7 6 5 4 3 2 1 0 perr ferr oerr rbfl tend tbep (initial value: 0000 11**) perr parity error flag 0: 1: no parity error parity error read only ferr framing error flag 0: 1: no framing error framing error oerr overrun error flag 0: 1: no overrun error overrun error rbfl receive data buffer full flag 0: 1: receive data buffer empty receive data buffer full tend transmit end flag 0: 1: on transmitting transmit end tbep transmit data buffer empty flag 0: 1: transmit data buffer full (transmit data writing is finished) transmit data buffer empty note:when an inttxd is generated, tbep flag is set to "1" automatically. uart1 receive data buffer rdbuf (01f93h) 7 6 5 4 3 2 1 0 read only (initial value: 0000 0000) uart1 transmit data buffer tdbuf (01f93h) 7 6 5 4 3 2 1 0 write only (initial value: 0000 0000) TMP88FW45AFG page 181 uart pin select register uartsel (01f90h) 7 6 5 4 3 2 1 0 txd sel rxd sel (initial value: **** **00) rxdsel rxd connect pin select 0: 1: rxd1 rxd2 r/w txdsel txd connect pin select 0: 1: txd1 txd2 note 1: do not change uartsel register during uart operation. note 2: set uartsel register before performing the setting terminal of a i/o port when changing a terminal. TMP88FW45AFG 15. asynchronous serial interface (uart1) 15.2 control page 182 15.3 transfer data format in uart1, an one-bit start bit (low level), stop bit (bit length selectable at high level, by uartcr1 15.4 transfer rate the baud rate of uart1 is set of uartcr1 15.6 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uartcr1 15.9 status flag 15.9.1 parity error when parity determined using the receive data bits differs from the received parity bit, the parity error flag uartsr figure 15-7 generation of overrun error note: receive operations are disabled until the overrun error flag uartsr figure 15-9 generation of transmit data buffer empty 15.9.6 transmit end flag when data are transmitted and no data is in tdbuf (uartsr 16. asynchronous serial interface (uart2) the TMP88FW45AFG has a asynchronous serial interface (uart) . it can connect the peripheral circuits through txd and rxd pin. txd and rxd pin are also used as the general port. for txd pin, the corresponding general port should be set output mode (set its output control register to "1" after its output port latch to "1"). for rxd pin, should be set input mode. rxd3 and txd3 are correspond to p81 and p80 pins as the connection pins with the peripheral circuits in the asynchronous serial interface (uart2). 16.1 configuration figure 16-1 uart2 (asynchronous serial interface) TMP88FW45AFG page 189 counter y a b c s s a b c d y e f g h uart status register uart control register 2 uart control register 1 transmit data buffer receive data buffer fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 fc/96 stop bit parity bit fc/2 6 fc/2 7 fc/2 8 baud rate generator transmit/receive clock 2 4 3 2 2 2 noise rejection circuit m p x transmit control circuit shift register shift register receive control circuit mpx: multiplexe r uartcr21 tdbuf2 rdbuf2 inttxd2 intrxd2 uartsr2 uartcr22 rxd3 txd3 inttc4 16.2 control uart2 is controlled by the uart2 control registers (uartcr21, uartcr22). the operating status can be monitored using the uart status register (uartsr2). uart2 control register1 uartcr21 (01f70h) 7 6 5 4 3 2 1 0 txe rxe stbt even pe brg (initial value: 0000 0000) txe transfer operation 0: 1: disable enable write only rxe receive operation 0: 1: disable enable stbt transmit stop bit length 0: 1: 1 bit 2 bits even even-numbered parity 0: 1: odd-numbered parity even-numbered parity pe parity addition 0: 1: no parity parity brg transmit clock select 000: 001: 010: 011: 100: 101: 110: 111: fc/13 [hz] fc/26 fc/52 fc/104 fc/208 fc/416 input inttc4 fc/96 note 1: when operations are disabled by setting uartcr21 |